We think you have liked this presentation. If you wish to download it, please recommend it to your friends in any social system. Share buttons are a little bit lower. Thank you!
Presentation is loading. Please wait.
Published byLandon Filbin
Modified about 1 year ago
1 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved.Copyright © 2011 SuVolta, Inc. All rights reserved. 1 Device Considerations for Low Power VLSI Circuits EDS Silicon Valley Chapter David Kidd Senior Director of Digital Design
2 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Transistor Variability Limits Chips Impact on Mobile System on Chip (SOC) Limited Low Power Design Techniques Where does Variability come from? New Transistor Alternatives to Reduce Variability Deeply Depleted Channel (DDC) technology Silicon Impact Outlook Taking advantage of Deeply Depleted Channel (DDC) technology in Mobile SOC Overview
3 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Multiple blocks with different performance requirements Integrated on the same die Different power modes – would like to run at different supplies Multiple V T transistors used to control leakage Single chip solution requires analog integration Need co-design of architecture, circuits and transistor technology for best solution What is needed in Mobile System on Chip?
4 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Limited benefit using voltage scaling (DVFS) Cannot overdrive much due to reliability and power restrictions Dynamically lowering voltage limited to mV Only lowering frequency leaves large leakage power “Run to hold” beats DVFS despite overhead Finicky SRAM memories High SRAM V MIN leaves no room for memory voltage scaling Many circuit tricks to improve V MIN and noise margins Design teams moved to dedicated power rail for SRAM Works for CPU – difficult in GPU Impacts power network integrity – more fluctuations Transistor variability limits chips Variability Limits Design & Architecture
5 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Global/Systematic/Manufacturing Variation Shifts all the transistors similarly Longer/shorter transistor lengths More (or less) implant energy and dose Will result in speed/power distribution Local/Random Variation Transistor next to each other vary widely Small number of dopants in transistor channel Random Dopant Fluctuation (RDF) Apparent in threshold voltage mismatch (σV T ) Impacts speed, leakage, SRAM & Analog Industry solution: Remove RDF using Undoped Channel What is the right silicon roadmap going forward? Transistor Variation Source of Chip Variation [#Transistors] Useable Yield Too slowToo hot
6 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. FinFET or TriGate Promises high drive current Manufacturing, cost, and IP challenge Doped channel to enable multi V T FDSOI Showing off undoped channel benefits Good body effect, but lack of multi V T capability Restricted supply chain DDC – Deeply Depleted Channel transistor Straight forward insertion into Bulk Planar CMOS Undoped channel to reduce random variability Good body effect and multi V T transistors Transistor Alternatives Source: IMEC Source: Fujitsu Textbook FinFET Source: GSS, Chipworks Intel TriGate
7 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Undoped or very lightly doped region Significantly reduced transistor random variability V T Lower leakage Better SRAM (I READ, lower V min & V ret ) Tighter corners Smaller area analog design Higher channel mobility (increased I eff, lower DIBL) Higher speed, improved voltage scaling V T setting offset region Enables multiple threshold voltages Screening region Strong body coefficient Bias bodies to tighten manufacturing distribution Body biasing to compensate for temperature and aging Deeply Depleted Channel™ (DDC) Transistor Benefits similar to FinFET in planar bulk CMOS *Example implementation
8 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Wells and VT Poly Spacers and LDDs Salicide Gate Metal Layers Blanket Epi STI Poly Spacers and LDDs Salicide Gate Metal Layers Wells and VT Foundry Standard Flow SuVolta Flow (example) New No new materials / No new tools STI Bulk Planar Foundry-Compatible Process
9 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Presented at IEDM 2011 TEM of DDC Transistor and STI 43.1nm S D
10 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Lower Transistor Variability Reduces Leakage Transistor variability is reflected in threshold voltage (V T ) distribution Leakage current is exponentially dependent on V T Lower V T variability ( V T ) reduces number of leaky low V T devices Power dissipation is dominated by low V T edge of distribution Smaller V T Less leakage power for digital and memory/SRAM High leakage tail High leakage tail dominates power 2.7x higher power (Model using 85mV subV T slope) High V T tail Slows down ICs [#Transistors] [Leakage Power] 65nm Silicon SRAM V T
11 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Nominal (TT) ring oscillator speed expected to be 400ps (A) Equivalent to having many similar critical paths in a chip V T variation will randomly affect paths within the same die limiting speed to 470ps Undoped channel reduces variability and increases mobility (B) 25% faster mean, 30% faster tail due to tighter distribution To match performance lower V DD until tails have same speed (C) Large impact on power due square dependence P=CV 2 f +IV Lower Transistor Variability Improves Speed 65nm Silicon Measurement (A) (B) (C)
12 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. SRAM memories built using 6-T SRAM cell Smallest transistors on every chip, worst V T mismatch Higher V DD is required to avoid failures SRAM blocks limit V DD scaling V min – lowest operating voltage limited by transistor mismatch Demonstrated SRAM to V min of 0.425V Standard SRAM macros No circuit “tricks” for low voltage operation Demonstrates potential for 50% voltage scaling Sub 0.5V V Min is Possible 300 mV Tester limit Industry Norm DDC
13 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. 40-60% improved matching for SRAM transistors Improved V T Matching Key for Low V MIN Baseline DDC Baseline DDC Baseline DDC Baseline DDC Presented at IEDM 2011
14 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. In analog circuits, matching is key Large transistors used to improve relative variability in current mirrors, differential pairs, etc. Better transistor matching allows for Area savings Higher performance Lower power Undoped channel improves R OUT higher gain OpAmp stage Matched bandwidth, gain, slewrate Over 50% smaller area (84 vs 190μm 2 ) 45% better input noise (176 vs 327 μV) Bandgap reference circuit Same accuracy achieved at half the size Design Examples Analog 450um 420um 210um 450um Baseline DDC Baseline DDC 10.9x17.4um 6.9x12.2um SuVolta sample layout
15 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Body Bias to fix systematic variation Speed-up (forward bias - FBB) slow parts Cool down (reverse bias - RBB) hot parts Increase manufacturing yield Body bias enables multiple modes of operation Active minimize power at every performance Standby leakage reduction, power gating DDC transistor provides 2-4x larger body factor Better Chips with Body Biasing Useable Yield Too slowToo hot RBBFBB TCAD prediction
16 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Inverter ring-oscillators (RO) fabricated at process corners 1.2V V DD and 0.9V V DD For each corner, DDC transistor RO is faster and lower power Using strong body coefficient to pull in corners Half the power (50% less power) while matching speed Half the Power at Matched Performance 65nm Silicon Measurement Baseline speed 50% power 100% power SS TT FF TT
17 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Better process control leads to tighter corners Manufacturing flow further reduces layout effects 1 sigma tighter wafer to wafer and within wafer variation for DDC Less overdesign as max paths and min (hold) paths are closer Faster design closure earlier tapeout shorter TTM Tighter Manufacturing Corners w/ DDC 11 22 33 V DD =1.2V V DD =0.9V POR 65nm Silicon Measurement
18 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Achieve half the speed at 1/6 the V DD Use body bias to compensate for temperature and aging Critical for low V DD operation Enable workable design window – avoid overdesign Voltage Scaling to 0.6V V DD 65nm Silicon Measurement Baseline DDC FF TT SS -83%
19 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Turbo Mode: DDC transistor achieves over 50% 1.2V V DD All corners for DDC run at 580MHz vs 370MHz for baseline This is HotChips – Go Faster! DVFSBaselineDDC V DD 1.2V0.6V0.9V1.05V1.2V Speed Power nm Silicon Measurement
20 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Same performance at 0.75V V DD as baseline at 0.9V V DD 30% lower power Alternatively 25% faster at same voltage Even better when using body bias to pull in corners 28nm and Beyond (silicon calibrated SPICE simulations)
21 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. CPU: Single thread performance critical Push frequency by temporarily raising voltage in turbo mode DVFS with body biasing becomes DVBFS GPU: High number of cores using small transistors Less overdesign due to lower delay variability Increase parallelism, lower voltage, body bias dynamically for more pixels/Watt Lower frequency blocks In addition to high V T transistors also run at lower voltage and optimal body bias Whole chip: Use body bias to adjust for manufacturing variation Take advantage of improved memory and analog performance Lowering variability while compatible with existing bulk planar silicon IP Applying DDC to Lower Variability in Mobile SOC
22 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved. Variability limits chips DDC transistor reduces random variability through its undoped channel DDC transistor’s strong body factor can be used to fix systematic variation and compensate for temperature variation DDC technology provides performance kicker from 90nm to 20nm Straight forward integration into existing nodes Compatible with existing bulk planar CMOS silicon IP Use existing CAD flow DDC technology brings back low power tools Large range DVFS Body biasing Low voltage operation Taking advantage of reduced variability DDC transistor in design and architecture will lead to next level in mobile SOC Conclusions
23 EDS Silicon Valley October 2012Copyright © 2012 SuVolta, Inc. All rights reserved.Copyright © 2011 SuVolta, Inc. All rights reserved. 23
PIDS: Poster Session 2002 ITRS Changes and 2003 ITRS Key Issues ITRS Open Meeting Dec. 5, 2002 Tokyo.
ITRS December 2003, Hsin-Chu Taiwan How Much Variability Can Designers Tolerate? Andrew B. Kahng ITRS Design ITWG December 1, 2003.
Design ITWG ITRS-2001 Grenoble Meeting April 27, 2001.
Background for Leakage Current Sept. 18, 2006 March 4, 2008.
6 February Design at the Top of the Semiconductor Foodchain: How Manufacturing Challenges Below 90nm Impact Circuits & Systems Rob A.
Georgia Tech Seminar 1 Keith A. Bowman Circuit Research Lab, Intel April 18, 2006 Keith A. Bowman Circuit Research Lab, Intel.
TDC ARCHITECTURES IN ASIC S Jorgen Christiansen CERN/PH-ESE 1.
Low Power Design From Technology Challenges to Great Products Barry Dennington Snr VP CTO/SoC Design Engineering October 5, 2006.
24 July 2002 Work In Progress – Not for Publication ITRS Test ITWG July 24 th, 2002.
ITRS Winter Public Conference, December 9, Seoul, Korea 1 Modeling and Simulation ITWG Jürgen Lorenz – Fraunhofer IISB – Chairperson M&S ITWG ITWG/TWG.
EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
CMOS Technology 1.Why CMOS 2.Qualitative MOSFET model 3.Building a MOSFET 4.CMOS logic gates Handouts: Lecture Slides.
18 July 2001 Work In Progress – Not for Publication 2001 ITRS Test Chapter ITRS Test ITWG Mike Rodgers Don Edenfeld.
DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference ITRS FEP Challenges Continued scaling will require the introduction of new materials.
ITRS Summer Public Conference, July 14, 2010, San Francisco, CA, USA 1 Modeling and Simulation ITWG Bert Huizing – NXP – European M&S ITWG and IRC member.
ITRS Summer Public Conference, July 15, San Francisco, CA, USA 1 Modeling and Simulation ITWG Jürgen Lorenz – Fraunhofer IISB – Chairperson M&S ITWG ITWG/TWG.
DESIGN FOR SEMICONDUCTOR RELIABILITY George Denes, Dipl.Eng. Senior Semiconductor Reliability Consultant.
On-Chip Communication Architectures Emerging On-Chip Interconnect Technologies ICS 295 Sudeep Pasricha and Nikil Dutt Slides based on book chapter 13 1©
Development of the Bandgap Voltage Reference Circuit, Featuring Dynamic- Threshold MOS Transistors (DTMOSTs) in 0.13um CMOS Technology. Vladimir Gromov.
1 Pier Francesco Manfredi Lawrence Berkeley National Laboratory - Berkeley, California (USA) Dipartimento di Fisica dellUniversità di.
Joint Design-Time and Post-Silicon Optimization for Analog Circuits: A Case Study Using High-Speed Transmitter Yiyu Shi, Wei Yao, Lei He, and Sudhakar.
Distributed Computing Dr. Eng. Ahmed Moustafa Elmahalawy Computer Science and Engineering Department.
A Case for Globally Shared-Medium On- Chip Interconnect Enhancing Effective Throughput for Transmission Line-Based Bus Aaron Carpenter, Jianyun Hu, Jie.
1 EC1313 – LINEAR INTEGRATED CIRCUITS Name : M.Venmathi Designation:Senior Lecturer Department:Electrical and Electronics Engineering College:Rajalakshmi.
ITRS Summer Conference 2007 Moscone Center San Francisco, USA 1 DRAFT – Work In Progress - NOT FOR PUBLICATION Modeling and Simulation ITWG Jürgen Lorenz.
The University of Texas at Austin EE382M VLSI-II Class Notes Foil # 1 Circuits Design for Low Power Kevin Nowka, IBM Austin Research Laboratory EE-382M.
Copyright © 2010 SpectraPlex – Presentation property of SpectraPlex, no reproduction without permission SpectraPlex High Performance Communications Technologies.
Field Effect Transistors. Introduction Two main types of FET: - JFET –Junction field effects transistor -MOSFET – Metal oxide semiconductor field effect.
UK SiGe Research Programme EPSRC Final Review Meeting, Thursday November 4th 2004 Electrical and Electronic Engineering Dept, Imperial College, Device.
Computer Systems Lecturer: Szabolcs Mikulas URL: Textbook: W. Stallings,
© 2016 SlidePlayer.com Inc. All rights reserved.