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Published byHaylie Atwill Modified about 1 year ago

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The High Voltage/High Power FET (HiVP) Amin K. Ezzeddine & Ho C. Huang Amcom Communications, Inc. Clarksburg, Maryland, USA

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Presentation Outline Why high voltage device? Traditional high voltage approaches New High Voltage/ High Power (HiVP) configuration Implementation of a 14V & 28V GaAs MMIC HiVP Conclusion

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Why High Voltage Device? Some applications need high voltage: –Phase arrays –Satellite transmitters –No DC-to-DC converter Low breakdown voltage in semiconductors materials such as: GaAs, AlGaAs, InP. High power

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FET High Voltage Configurations Traditional high voltage device configurations: –DC series/ RF parallel –DC series/ multi-stage New High Voltage/high Power device (HiVP)

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DC Series/RF Parallel Configuration INPUT MATCHING OUTPUT MATCHING INPUT MATCHING INPUT MATCHING INPUT MATCHING OUTPUT MATCHING OUTPUT MATCHING OUTPUT MATCHING Power Divider Power Combiner V gg V ds 2V ds 3V ds V dd = 4V ds RF IN RF OUT Choke Bypass

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DC-Series/Cascaded-Stages Configuration RF out OUTPUT MATCHING INPUT MATCING V ds 2V ds INTERSTAGE MATCHING V gs RF in Choke Bypass

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New High Voltage/ High Power (HiVP) Equivalent performance to a single device: - Efficiency - Power Higher gain High voltage bias Scaled I-V characteristics Power combiner

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4-Cell High Voltage/ High Power (HiVP) OUTPUT MATCHING INPUT MATCHING VgsVgs V d3 =3V ds V dd = 4V ds RF IN RF OUT V d2 =2V ds V d1 =V ds FET1 (W/4) FET2 (W/4) FET3 (W/4) FET4 (W/4) C1C1 C2C2 C3C3 R4R4 R3R3 R2R2 R1R1 V g4 =3V ds + V gs V g3 =2V ds + V gs V g2 =V ds + V gs V g1 =V gs

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I-V Characteristics of a 4-Cell (4 x 3mm) HiVP Device

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4-Cells HiVP Voltage Waveforms V in V d3 =3V m V dd = 4V m V d2 =2V m V d1 =V m C1C1 C2C2 C3C3 R4R4 R3R3 R2R2 R1R1 Z opt

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Impedance Optimization of Common Gate FET Z source, N 1/g m (C gs + C N ) / C N g m is FET transconductance C gs is FET gate-to-source capacitance Z opt, N+1 DrainSource C N+1 Gate Drain Source CNCNCNCN Z source, N Z opt, N Z opt, N = Z source, N+1 Gate (N+1) th FET N th FET

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HiVP Configuration Features High voltage bias: V dd = V ds x N Lower Current by 1/N factor compared to regular FET with equivalent periphery Higher optimum output impedance by N 2 factor Higher input impedance Higher gain by factor of N Broadband matching Simple & compact configuration Concept applicable to LDMOS and MOSFET to achieve very high power

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Power & IP3 for 14V Hybrid HiVP at 1GHz P 1dB =35dBm Efficiency = 25% IP3 = 1.0GHz

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14V/2-Cells HiVP MMIC ( 2 x 2mm device) Chip Layout S-Parameters P 1dB =31dBm Efficiency = 35% IP3 = 3.5GHz

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Pout & Efficiency of 2 x 2mm HiVP at 3.5GHz

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IP3 & IP5 of 2 x 2mm HiVP at 3.5GHz

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28V/4-Cells HiVP MMIC (4 x 1mm device ) Chip Layout S-Parameters P 1dB =31dBm Efficiency = 32% IP3 = 1GHz

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28V/4-Cells HiVP in Parallel (4 x 3mm device) Package Device4 x 3mm Chip P 1dB =35dBm Efficiency = 27% IP3 = 2.15GHz

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Power & Efficiency of 4 x 3mm HiVP at 2.15GHz

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IP3 of a 4 x 3mm HiVP at 2.15GHz

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IP3 at 2.15GHz for 4 x 3mm HiVP versus 12 mm FET

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24V/4-Cell High Power pHemt HiVP (4 x24mm) 4 x 6mm Chip 4 x 24mm Chip P 1dB =43dBm Efficiency = 30% IP3 = 1.5GHz

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Power & Efficiency of 4 x 24mm pHemt HiVP at 1.5GHz

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IP3 of 4 x 24mm pHEMT HiVP at 1.5GHz

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Conclusion A simple DC series/RF series device (HiVP) for high voltage operation is presented This simple new device behaves as an RF combiner New device has good linearity and broadband performance HiVP concept could be applied to GaN and Silicon FETs to push the power to kW ranges

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