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**High efficiency Power amplifier design for mm-Wave**

Seyed Yahya Mortazavi

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**Outline Introduction: Power amplifier (PA) Metrics**

Class A, AB, B, C Pas High efficiency Class F Pas mm-Wave PA applications mm-Wave PA challenges and survey Our Designs: Steps, Simulations results Conclusions and future works

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**Power amplifier basics**

Metrics: Gain: 𝐺= 𝑃 𝑜𝑢𝑡,1𝑓 𝑃 𝑖𝑛 Efficiency: 𝜂= 𝑃 𝑜𝑢𝑡,1𝑓 𝑃 𝑑𝑐 = 𝑉 𝑚 𝐼 𝑚 2 𝑉 𝐶𝐶 𝐼 𝐼 = 𝑃 𝑜𝑢𝑡,1𝑓 𝑃 𝑑𝑖𝑠𝑠 + 𝑃 𝑜𝑢𝑡,1𝑓 Power Added Efficiency: 𝑃𝐴𝐸= 𝜂 𝑎𝑑𝑑𝑒𝑑 = 𝑃 𝑜𝑢𝑡,1𝑓 − 𝑃 𝑖𝑛 𝑃 𝑑𝑐 =𝜂(1− 1 𝐺 )

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**Power amplifier basics**

AB C B A AB B C VBE VCE Gain and Efficiency trade-off: Class A: highest gain and linearity Class C: highest efficiency ….. A AB B C time

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**PA basics IC IC0 , IC1 CA ωt Conduction angle (CA) 𝐼𝐶1 𝐼𝐶0 𝑃𝑑𝑐∝𝐼𝐶0**

𝑃𝑙𝑜𝑎𝑑∝𝐼𝐶1 𝜂= 1 2 𝐼𝐶1 𝐼𝐶0 𝑉𝑚 𝑉𝑑𝑐 max 𝑉𝑚 = 1 2 𝑉𝑑𝑐−𝑉𝐵𝑅−𝑉𝐾𝑛𝑒𝑒 Conduction angle (CA)

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**PA basics High efficiency PAs Class E, switching PAs Class F ω 0 t**

𝑍 𝐿,𝑛𝑓 = 𝑍 𝐿,𝑛𝑓 𝑒 −𝑗 𝜑 𝑛 𝑖 𝑐 𝑣 𝑐 High efficiency PAs Class E, switching PAs Class F 𝜂= 𝑃 𝑜𝑢𝑡,1𝑓 𝑃 𝑑𝑐 = 𝑃 𝑜𝑢𝑡,1𝑓 𝑃 𝑑𝑖𝑠𝑠 + 𝑃 𝑜𝑢𝑡,1𝑓 + 𝑛=2 ∞ 𝑃 𝑜𝑢𝑡,𝑛𝑓 𝑍 𝐿,1𝑓 = 𝑅 𝐿,𝑜𝑝𝑡 , 𝑍 𝐿,(2𝑛)𝑓 =0, 𝑍 𝐿,(2𝑛+1)𝑓 =∞ 𝑖 𝑐 𝑡 = 𝐼 0 + 𝐼 1𝑓 . 𝑐𝑜𝑠 𝜔 0 𝑡 + 𝐼 2𝑓 . sin 2𝜔 0 𝑡 +… +𝐼 2𝑛 𝑓 . sin 2𝑛 𝜔 0 𝑡 𝑣 𝑐 𝑡 = 𝑉 0 + 𝑉 1𝑓 . cos 𝜔 0 𝑡 + 𝑉 3𝑓 . cos 3𝜔 0 𝑡 +… +𝑉 (2𝑛+1) 𝑓 . cos 2𝑛+1 𝜔 0 𝑡 𝑍 𝐿,1𝑓 = 𝑅 𝐿,𝑜𝑝𝑡 , 𝑍 𝐿,(2𝑛)𝑓 =∞, 𝑍 𝐿,(2𝑛+1)𝑓 =0 ω 0 t

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**Class F PAs Vce Vce time time Maximally Flat (F3)**

Maximum Efficiency (F3) time Uses harmonics to Reduce Vce for same fundamental: same output power with less dissipated power. F3: 𝑣 𝑐𝒆 𝑡 = 𝑉 0 + 𝑉 1𝑓 . cos 𝜔 0 𝑡 + 𝑉 3𝑓 . cos 3𝜔 0 𝑡 F2: 𝑣 𝑐𝒆 𝑡 = 𝑉 0 + 𝑉 1𝑓 . cos 𝜔 0 𝑡 + 𝑉 𝟐𝑓 . cos 𝟐𝜔 0 𝑡 F35: 𝑣 𝑐𝒆 𝑡 = 𝑉 0 + 𝑉 1𝑓 . cos 𝜔 0 𝑡 + 𝑉 3𝑓 . cos 3𝜔 0 𝑡 + 𝑉 𝟓𝑓 . cos 𝟓𝜔 0 𝑡 F24: 𝑣 𝑐𝒆 𝑡 = 𝑉 0 + 𝑉 1𝑓 . cos 𝜔 0 𝑡 + 𝑉 𝟐𝑓 . cos 𝟐𝜔 0 𝑡 + 𝑉 𝟒𝑓 . cos 𝟒𝜔 0 𝑡

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**Class F PA Vm/Vdc Im/Idc 1.12, 1.15 Pi/2, 1.33,1.41 Pi/4 1.17,1.207**

1.42,1.5 Pi/4

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**mm-Wave PAs Application**

Data Communication (based on FCC frequency allocation): 59-64 GHz (V-band), 71-76 GHz, 81-86 GHz (E-bands), and GHz (W-bands) 77 GHz Automotive Radars > 77 GHz Active Imaging: Security gates, Medical Imaging applications, Radar systems,

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**Si-based mm-Wave PAs Low Break-down voltage:**

Reduces output voltage swing: smaller output power or gain More sensitive to parasitics: Parasitics have Lower impedance as frequency increase Close to fT of transistor: Lower power gain and PAE IC BVCO VCE

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**Si-based mm-wave PAs PAE (%) Pout (dBm) Pout (dBm) PAE (%)**

CMOS And SiGe PAs PAE (%) Pout (dBm) Frequency (GHz) Frequency (GHz) SiGe PAs PAE (%) Pout (dBm) Frequency (GHz) Frequency (GHz)

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**Si-based mm-wave PAs Gain(dB) Gain (dB) CMOS And SiGe PAs SiGe PAs**

Frequency (GHz) SiGe PAs Gain (dB) Frequency (GHz)

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Review- VCE > BVCO RFIC-2008 79GHz, PAE~ 13.5%, Pout ~ 17.7 dBm, Gain~14 dB, Class AB The external base impedance seen from Q1, Q2, and Q3 is small at Wband frequencies. The resulting effective collectoremitter breakdown voltage allows the output voltage at the collectors to peak above 4.2 V, a factor of 2.5 improvement over BVceo.

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Review- Cascoding TMTT-2011 77GHz, PAE~ 7.5%, Pout ~ 15 dBm, Gain~22.5 dB, Class AB the CAS topology was preferred to achieve a higher stable gain, better reverse isolation, and improved robustness. A large output voltage swing is tolerated by the CB ( > BVCO) if it is driven with a low base resistance.

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Review- Current reuse TMTT-2012 77GHz, PAE~ 9%, Pout ~ 14.5 dBm, Gain~25 dB, Class AB Current reuse at Driver stage

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PA design Steps DC simulations for Knee and BVCO voltages for estimating maximum voltage swing (Vpp), Calculation and simulations for finding transistor size and DC bias current for Class A PA regarding Vpp and required Pout , Current density for max fT is 8~11 mA/um for SiGe HBTs. Input matching for selected size and bias point, Iterative Load-pull simulations for determining parasitic capacitance (Cce or Cp) and verifying Ropt , Changing bias from class A to class AB for max efficiency and Gain, Adjusting Ropt Output matching,

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**PA design Steps Bias for class A,**

Ropt for Load-line Power matching vs conjugate power matching

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**PA design Steps Input matching and load pull (94GHz PA)**

Load-pull simulation is done for different Lp to get the optimum point over pure real Impedance

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**PA design Steps Changing bias point from A to AB**

PAE (%) PAE (%) VBE VBE Pin = 11 dBm Rout=38Ω Pin (dBm) Rout (Ω) Gain (dB) PAE (%) Rout=38Ω, Pin=0, 11 dBm VBE (mV)

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**Utilizing 3rd H for efficiency (F3)**

𝜂= 𝑃 𝑜𝑢𝑡,1𝑓 𝑃 𝑑𝑐 = 𝑃 𝑜𝑢𝑡,1𝑓 𝑃 𝑑𝑖𝑠𝑠 + 𝑃 𝑜𝑢𝑡,1𝑓 + 𝑃 𝑜𝑢𝑡,3𝑓 𝑃 𝑑𝑖𝑠𝑠 + 𝑃 𝑜𝑢𝑡,1𝑓 + 𝑃 𝑜𝑢𝑡,3𝑓 𝐹3 < (𝑃 𝑑𝑖𝑠𝑠 + 𝑃 𝑜𝑢𝑡,1𝑓 + 𝑃 𝑜𝑢𝑡,3𝑓 ) 𝐴𝐵

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**Utilizing 3rd H for efficiency (F3)**

𝐿 1 = 𝜔 𝐶 𝑝 𝐿 2 = 𝜔 𝐶 𝑝 𝐶 2 =2.4∙ 𝐶 𝑝

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**Utilizing 3rd H for efficiency (F3)**

Pdissp (mW) Pout (dBm) Pin (dBm) Pin (dBm) F3-Harmonic Control F3-filter AB PAE (%)

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**Utilizing 3rd H for efficiency (F3)**

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**Utilizing 3rd H for efficiency (F3)**

Pdissp (mW) Pout (dBm) Pin (dBm) Pin (dBm) PAE (%) Pin (dBm)

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**94 GHz 1-Stage Class-F PA (VCC = 1.3V): Schematic**

Class-F, 1-stage design: 2nd & 3rd harmonic controls Harmonic filter: high-Z for fund & 3rd-harmonic, low-Z for 2nd-harmonic OP-1dB: ~10 dBm, Psat: ~11.5 dBm PAE: max %

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**94 GHz 1-Stage Class-F PA (VCC = 1.3V): Simulations**

P-1dB = 7.7dBm S21 Pout (dBm) PAEmax =15.3% PAE (%) S11 S-parameter (dB) S22 Pin (dBm) Freq (GHz)

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**94 GHz 1-Stage Class-F PA (VCC = 1.3V): Layout**

gnd VBB VCC gnd gnd gnd rfIn rfOut gnd gnd Size: 535μm x 390μm

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**94 GHz 1-Stage Class-F PA (VCC = 2.2V): Schematic**

Class-F, 1-stage design: 2nd & 3rd harmonic controls Harmonic filter: high-Z for fund & 3rd-harmonic, low-Z for 2nd-harmonic OP-1dB: ~15 dBm, Psat: ~16 dBm PAE: max %

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**94 GHz 1-Stage Class-F PA (VCC = 2.2V): Simulations**

PAEmax =21.8% S21 Pout (dBm) P-1dB = 11.9dBm PAE (%) S-parameter (dB) S22 S11 Pin (dBm) Freq (GHz)

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**94 GHz 1-Stage Class-F PA (VCC = 2.2V): Layout**

gnd VBB VCC gnd gnd gnd rfIn rfOut gnd gnd Size: 530μm x 400μm

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**94 GHz 2-Stage Class-F PA: Schematic**

Class-F, 2-stage design: 2nd & 3rd harmonic controls Harmonic filter: high-Z for fund & 3rd-harmonic, low-Z for 2nd-harmonic OP-1dB: ~16 dBm, Output Psat: ~17 dBm PAE: max %

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**94 GHz 2-Stage Class-F PA : Simulations**

PAEmax =22% S21 P-1dB = 9.1dBm Pout (dBm) PAE (%) S-parameter (dB) S22 S11 Pin (dBm) Freq (GHz)

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**94 GHz 2-Stage Class-F PA : Layout**

gnd VBB1 VCC1 gnd gnd gnd rfIn rfOut gnd gnd gnd VCC2 VBB2 gnd Size: 670μm x 490μm

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**60 GHz 1-Stage Class-F PA with coupled harmonic control: Schematics**

Class-F, 1-stage design: 2nd & 3rd harmonic controls Harmonic filter: high-Z for fund & 3rd-harmonic, low-Z for 2nd-harmonic OP-1dB: ~12.8 dBm, Psat: ~15 dBm PAE: max %

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**60 GHz 1-Stage Class-F PA with coupled harmonic control: Simulations**

PAEmax =25.5% S21 Pout (dBm) P-1dB = 7.7dBm PAE (%) S-parameter (dB) S11 S22 Pin (dBm) Freq (GHz) These are simulation results including layout sonnet EM-model. Single stage design has ~15 dBm Psat with 25-26% PAE.

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**60 GHz 1-Stage Class-F PA with coupled harmonic control: Layout**

gnd VBB VCC gnd gnd gnd rfIn rfOut gnd gnd Size: 710μm x 410μm

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**Design Summary 94GHz PAE (%) IP1dB (dBm) Psat (dBm) Gain (dB)**

1stage-1.3V 15.3 7.7 12.5 3.8 1stage-2.2V 21.8 11.9 17 4 2stage 22 9.1 7.8 60GHz PAE (%) P1dB (dBm) Psat (dBm) Gain (dB) 1stage-1.3V 25.8 5.5 12.5 6.5 1stage-2.2V 29 9.7 17 7 2stage 28.5 4.2 16 11.5 33GHz PAE (%) P1dB (dBm) Psat (dBm) Gain (dB) 1stage-1.3V 30 2.5 11 7 1stage-2.2V 40 4 15 10

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**Si-based mm-wave PAs SiGe PAs PAE (%) Pout (dBm) Gain (dB)**

Frequency (GHz) Frequency (GHz) Gain (dB) Frequency (GHz)

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**Future Works Increasing gain using efficient driving stages**

Increasing gain using Power combining techniques Improving quality factor of Capacitors using MOM caps Class E PAs

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**60 GHz 1-Stage Class-F PA (VCC = 1.3V): Schematic**

Class-F, 1-stage design: 2nd & 3rd harmonic controls Harmonic filter: high-Z for fund & 3rd-harmonic, low-Z for 2nd-harmonic OP-1dB: ~11 dBm, Psat: ~12.5 dBm PAE: max %

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**60 GHz 1-Stage Class-F PA (VCC = 1.3V): Simulations**

PAEmax =25.8% S21 Pout (dBm) PAE (%) P-1dB = 5.5dBm S-parameter (dB) S11 S22 Pin (dBm) Freq (GHz) These are simulation results including layout sonnet EM-model. Single stage design has ~12.5 dBm Psat with 25-26% PAE.

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**60 GHz 1-Stage Class-F PA (VCC = 1.3V): Layout**

gnd VBB VCC gnd gnd gnd rfIn rfOut gnd gnd Size: 610μm x 410μm

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**60 GHz 1-Stage Class-F PA (VCC = 2.2V): Schematic**

Class-F, 1-stage design: 2nd & 3rd harmonic controls Harmonic filter: high-Z for fund & 3rd-harmonic, low-Z for 2nd-harmonic OP-1dB: ~9.7 dBm, Psat: ~15 dBm PAE: max %

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**60 GHz 1-Stage Class-F PA (VCC = 2.2V): Simulations**

PAEmax =29% S21 Pout (dBm) P-1dB = 9.7dBm S-parameter (dB) PAE (%) S22 S11 Freq (GHz) Pin (dBm) These are simulation results including layout sonnet EM-model. Single stage design has ~16 dBm Psat with 29-30% PAE.

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**60 GHz 1-Stage Class-F PA (VCC = 2.2V): Layout**

gnd VBB VCC gnd gnd gnd rfIn rfOut gnd gnd Size: 575μm x 410μm

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**60 GHz 2-Stage Class-F PA : Schematic**

Class-F, 2-stage design: 2nd & 3rd harmonic controls Harmonic filter: high-Z for fund & 3rd-harmonic, low-Z for 2nd-harmonic OP-1dB: ~15 dBm, Psat: ~16 dBm PAE: max %

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**60 GHz 2-Stage Class-F PA : Simulations**

PAEmax =28.5% S21 P-1dB = 4.2dBm Pout (dBm) PAE (%) S-parameter (dB) S22 S11 Pin (dBm) Freq (GHz)

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**60 GHz 2-Stage Class-F PA : Layout**

VBB1 VCC1 gnd rfIn rfOut VBB2 VCC2 Size: 900μm x 400μm

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**33 GHz 1-Stage Class-F PA (VCC = 1.3V): Schematic**

Class-F, 1-stage design: 2nd & 3rd harmonic controls Harmonic filter: high-Z for fund & 3rd-harmonic, low-Z for 2nd-harmonic OP-1dB: ~11 dBm, Psat: ~10.5 dBm PAE: max %

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**33 GHz 1-Stage Class-F PA (VCC = 1.3V): Simulations**

PAEmax =30% S21 Pout (dBm) PAE (%) P-1dB = 2.5dBm S-parameter (dB) S22 S11 Pin (dBm) Freq (GHz) These are simulation results including layout sonnet EM-model. Single stage design has ~10.5 dBm Psat with 29-30% PAE.

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**33 GHz 1-Stage Class-F PA (VCC = 1.3V): Layout**

gnd VBB VCC gnd gnd gnd rfIn rfOut gnd gnd Size: 615μm x 440μm

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**33 GHz 1-Stage Class-F PA (VCC = 2V): Schematic**

Class-F, 1-stage design: 2nd & 3rd harmonic controls Harmonic filter: high-Z for fund & 3rd-harmonic, low-Z for 2nd-harmonic OP-1dB: ~9.7 dBm, Psat: ~15 dBm PAE: max %

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**33 GHz 1-Stage Class-F PA (VCC = 2V): Simulations**

PAEmax =40% S21 Pout (dBm) S-parameter (dB) P-1dB = 4dBm PAE (%) S22 S11 Freq (GHz) Pin (dBm) These are simulation results including layout sonnet EM-model. Single stage design has ~15 dBm Psat with 39-40% PAE.

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**33 GHz 1-Stage Class-F PA (VCC = 2V): Layout**

gnd VBB VCC gnd gnd gnd rfIn rfOut gnd gnd Size: 620μm x 440μm

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**60 GHz 1-Stage Class-F PA with coupled harmonic control: Schematics**

Class-F, 1-stage design: 2nd & 3rd harmonic controls Harmonic filter: high-Z for fund & 3rd-harmonic, low-Z for 2nd-harmonic OP-1dB: ~12.8 dBm, Psat: ~15 dBm PAE: max %

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**60 GHz 1-Stage Class-F PA with coupled harmonic control: Simulations**

PAEmax =25.5% S21 Pout (dBm) P-1dB = 7.7dBm PAE (%) S-parameter (dB) S11 S22 Pin (dBm) Freq (GHz) These are simulation results including layout sonnet EM-model. Single stage design has ~15 dBm Psat with 25-26% PAE.

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**60 GHz 1-Stage Class-F PA with coupled harmonic control: Layout**

gnd VBB VCC gnd gnd gnd rfIn rfOut gnd gnd Size: 710μm x 410μm

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**33 GHz 1-Stage Class-F PA with coupled harmonic control: Schematics**

Harmonic filter Z-matching biasing Class-F, 1-stage design: 2nd & 3rd harmonic controls Harmonic filter: high-Z for fund & 3rd-harmonic, low-Z for 2nd-harmonic OP-1dB: ~12.8 dBm, Psat: ~15 dBm PAE: max %

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**33 GHz 1-Stage Class-F PA with coupled harmonic control: Simulations**

PAEmax =32% S21 Pout (dBm) PAE (%) S-parameter (dB) P-1dB = 10.2dBm S22 S11 Pin (dBm) Freq (GHz) These are simulation results including layout sonnet EM-model. Single stage design has ~12.5 dBm Psat with 31-32% PAE.

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**33 GHz 1-Stage Class-F PA with coupled harmonic control: Layout**

gnd VBB VCC gnd gnd gnd rfIn rfOut gnd gnd Size: 670μm x 430μm

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**Utilizing 3rd H for efficiency (F3)**

Pdissp (mW) Pout (dBm) Pin (dBm) Pin (dBm) F3-filter F3-Harmonic Control AB F3-Harmonic Control F3-filter AB Vce (V) Ic (mA) PAE (%) time (ps)

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