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ECE 663 MOSFET SCALING. ECE 663 Scaling of switches.

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Presentation on theme: "ECE 663 MOSFET SCALING. ECE 663 Scaling of switches."— Presentation transcript:


2 ECE 663 Scaling of switches

3 ECE 663 Moore’s Law economics… Moore’s Law - #DRAM Bits per chip doubles every 18 months ~25% bigger chips/wafers ~25% design improvements ~50 % Lithography – ability to print smaller features Exponentials !! (461 B tonnes)

4 Exponential growth: Natural law of economics vs self-fulfilling prophecy? Kryder’s Law for energy storage Malthus’ Law Solid State Lighting

5 More natural curves Hubbert Curve

6 ECE 663 When the chip’s down… With feature size shrink of  2 (typical generation) –2x #transistors/unit area –2X Higher speed (f max ) –Fixed cost per wafer  Smaller (2x), Faster (2x), cheaper – strong economic driving force  30% improvement in cost per function per year

7 ECE 663

8 CMOS Device Scaling ParametersVariablesScaling Factor DimensionsW,L,x ox,x j 1/ PotentialsV ds,V gs 1/k Doping ConcentrationN 2 /k Electric FieldE /k CurrentI ds /k 2 Gate DelayT k/ 2 =dimensional scaling factor k=supply voltage scaling factor

9 ECE 663 Constant Field Scaling: keep E constant in channel k= Constant Voltage Scaling: keep supply voltage constant k=1(used for submicron scaling) ParametersConst FieldConst Volt Dimensions 1/ Potentials 1/ 1 Doping Concentration 2 Electric Field1 Current 1/ Gate Delay 1/ 1/ 2

10 ECE 663 Short Channel Effects – punch through

11 ECE 663 Threshold Voltage Roll-off/DIBL

12 ECE 663 Scaling Rule of Thumb L min minimum gate length for “long channel” behavior Computer simulations, experiments: X o gate oxide thickness (Å) L min,W s,W D,r j (S/D junction depth) in microns S/D junctions, depletion depths (doping), oxide thickness must scale with minimum gate length rjrj WsWs xoxo rjrj WDWD L

13 ECE 663 Short Channel MOSFET Geometry How much channel charge does the gate control?

14 ECE 663 Threshold Voltage Shift Threshold Voltage Long Channel transistor:

15 ECE 663 Short Channel transistor: charge in trapezoidal region Charge control region…

16 ECE 663 A little geometry rjrj WDWD W max rjrj

17 ECE 663 A little algebra 

18 ECE 663 Threshold shift Shallow junctions, low doping…

19 ECE 663 But this increases the contact resistances… Thus, raised Source-Drain

20 ECE 663 Charge sharing creates DIBL

21 ECE 663 Charge sharing creates DIBL 3D Simulation of Nanowire FETs using Quantum Models Vijay Sai Patnaik, Ankit Gheedia and M. Jagadesh Kumar The authors are with the Department of Electrical Engineering, Indian Institute of Technology, Huaz Khas, New Delhi 110 016, India (Email:

22 ECE 663 Narrow Gate Width Effect Volume of depletion region gets bigger due to “end caps” Takes more gate voltage to invert the channel W max Z

23 ECE 663 Narrow Gate Effect Threshold voltage gets bigger with decreasing Z

24 ECE 663 Punch-Through rjrj WsWs xoxo rjrj WDWD L rjrj WsWs xoxo rjrj WDWD L +V D ++V D n-p-n BJT S&D depletions touch – punch through e-e-

25 ECE 663 Punch Through Electrons can flow from source to drain (no more back to back junctions) (n-channel enhancement mode) I D  V D 2 Drain current no longer controlled by gate Transistors won’t “turn off” General “Cure” – high dose implant in sub-gate region to make narrower depletion widths Higher substrate doping increases parasitic capacitances

26 ECE 663 Oxide Charging Carriers accelerated toward Drain/depletion can have sufficient energy to escape into the oxide Neutral traps (defects) in the oxide trap charge Leads to long term shift in characteristics in long-channel Short-channel – more of the gate oxide is near the drain – big effect – big V T and g m effects - device failure N gradient

27 ECE 663 Lightly Doped Drain Structure - LDD Reduced N gradient – smaller electric field near drain – fewer “hot” electrons into oxide n - to avoid large fields and hot electrons, n + to get Ohmic contacts (still need to avoid punch-through) n-n- n+

28 ECE 663 Lightly Doped Drain Structure - LDD Reduced N gradient – smaller electric field near drain – fewer “hot” electrons into oxide n - to avoid large fields and hot electrons, n + to get Ohmic contacts n-n- n+ LDD from Fujitsu

29 ECE 663 Vanilla CMOS 2-level metal 16-masks

30 ECE 663 LDD Structure

31 ECE 663 Halo Implants Local heavy substrate doping for punch-through control leaving channel lightly doped for threshold control

32 ECE 663 Velocity Saturation

33 ECE 663 Velocity Saturation Effect – supressed drain current MeasurementCalculation w/Calculation w/oVelocity Saturation

34 ECE 663

35 Strained Si

36 ECE 663 Strained Si

37 ECE 663 Ge Mosfets

38 ECE 663 CMOS Inverter Latch-up – p-well technology

39 ECE 663 SOI No body effect parameter (depletion width fixed) Junction to substance parasitic capacitance small (faster switch!) No latch-up between NMOS and PMOS (no substrate)

40 ECE 663 Band diagram in SOIs

41 ECE 663 SOI S = (MkT/q)ln(10), M = 1+ C p /C ox

42 ECE 663 Kink effect in PDSOI At high drain bias, holes accelerated at reverse biased drain-body junction through impact ionization. Floating body gets charged up, and suddenly reduces gate threshold voltage Saraya et al

43 ECE 663 Gate Depletion Solution: Metal Gates

44 ECE 663


46 Gordon Moore Intel as ISCC 2003 Multi-Gates

47 ECE 663 Gordon Moore Intel as ISCC 2003

48 ECE 663

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