Download presentation

Presentation is loading. Please wait.

Published byNataly Tamblyn Modified about 1 year ago

1
CS1Q Computer Systems Lecture 12 Simon Gay

2
Lecture 12CS1Q Computer Systems - Simon Gay 2 Design of Sequential Circuits The systematic design of sequential circuits is not part of the syllabus of the course, so this lecture is for general interest. You are not expected to know the material in this lecture for the exam. By looking at design techniques for sequential circuits, we can complete the link between finite state machines and digital circuits. Two examples: 1. a system which produces a sequence of outputs, driven by a clock 2. the accepting finite state machine from Lecture 13 Slide 31.

3
Lecture 12CS1Q Computer Systems - Simon Gay 3 The Prime Number Machine The first example is a circuit which outputs the sequence 2, 3, 5, 7, 11, 13 as 4 bit binary numbers. The circuit will be driven by a clock, so that each clock pulse causes the output to change to the next number in the sequence, returning to 2 after 13. The sequence of outputs in binary is 0010, 0011, 0101, 0111, 1011, 1101 There are two possible approaches to the design, and we will look at them both.

4
Lecture 12CS1Q Computer Systems - Simon Gay 4 PNM First Design Idea: store the output word in a 4 bit register.

5
Lecture 12CS1Q Computer Systems - Simon Gay 5 PNM First Design Idea: store the output word in a 4 bit register.

6
Lecture 12CS1Q Computer Systems - Simon Gay 6 PNM First Design Assume that we have a 4 bit register as a standard component. At each clock pulse, the values of the inputs D3,D2,D1,D0 are stored in the register, replacing the previous stored values. The outputs Q3,Q2,Q1,Q0 are the stored values. The Reset input sets the stored value to 0000, asynchronously. Q3Q2Q1Q0 D3D2D1D0 ResetClock This register can be built from four D flipflops with reset inputs.

7
Lecture 12CS1Q Computer Systems - Simon Gay 7 PNM First Design The Reset input will set the stored value to 0000, but this is not one of the numbers in the sequence. Suppose we want Reset to make the output be A simple solution is to invert the Q1 output. Q3Q2Q1Q0 D3D2D1D0 ResetClock not output This means that the sequence of values for Q3,Q2,Q1,Q0 is 0000, 0001, 0111, 0101, 1001, 1111

8
Lecture 12CS1Q Computer Systems - Simon Gay 8 Q3Q2Q1Q0D3D2D1D XXXX PNM First Design All we need to do now is design a combinational circuit which inputs Q3,Q2,Q1,Q0 and outputs D3,D2,D1,D0 (these are the values which will be stored in the register at the next clock cycle). Q3Q2Q1Q0D3D2D1D XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

9
Lecture 12CS1Q Computer Systems - Simon Gay 9 PNM First Design Karnaugh maps are a convenient way of handling the don’t care (X) values. Leaving the X squares blank, we can cover the 1s with rectangles which may also contain blank squares. Karnaugh map for D3: Q3 Q1 Q2 Q0

10
Lecture 12CS1Q Computer Systems - Simon Gay 10 PNM First Design Karnaugh maps are a convenient way of handling the don’t care (X) values. Leaving the X squares blank, we can cover the 1s with rectangles which may also contain blank squares. Karnaugh map for D2: Q3 Q2 Q0 Q1

11
Lecture 12CS1Q Computer Systems - Simon Gay 11 PNM First Design Karnaugh maps are a convenient way of handling the don’t care (X) values. Leaving the X squares blank, we can cover the 1s with rectangles which may also contain blank squares. Karnaugh map for D1: Q3 Q2 Q0 Q1

12
Lecture 12CS1Q Computer Systems - Simon Gay 12 PNM First Design Karnaugh maps are a convenient way of handling the don’t care (X) values. Leaving the X squares blank, we can cover the 1s with rectangles which may also contain blank squares. Karnaugh map for D0: Q3 Q2 Q0 Q1

13
Lecture 12CS1Q Computer Systems - Simon Gay 13 PNM First Design We end up with the following design (exercise: complete the circuit). Q3Q2Q1Q0 D3D2D1D0 ResetClock combinational circuit not output

14
Lecture 12CS1Q Computer Systems - Simon Gay 14 PNM Second Design The first design works but has a couple of undesirable features: a 4 bit register is used, but there are only 6 states and therefore only 3 bits of storage should be necessary it seems to be a fluke that the “Reset problem” can be solved so easily; this technique might be hard to generalise The idea for the second design is to assume that we have a 3 bit counter as a standard component. It has a clock input and an asynchronous reset input. Q2Q1Q0 Reset Clock

15
Lecture 12CS1Q Computer Systems - Simon Gay 15 PNM Second Design Assuming that we make use of states 0 to 5 (i.e. 000 to 101) of the counter, we need a circuit to calculate the outputs P3,P2,P1,P0 according to this truth table: Q2Q1Q0P3P2P1P XXXX XXXX Easy to design the circuit for P3,P2,P1,P0 (exercise).

16
Lecture 12CS1Q Computer Systems - Simon Gay 16 PNM Second Design Karnaugh map for P3: Q1 Q2 Q0 Q1

17
Lecture 12CS1Q Computer Systems - Simon Gay 17 PNM Second Design Karnaugh map for P2: Q1 Q2 Q1 Q0

18
Lecture 12CS1Q Computer Systems - Simon Gay 18 PNM Second Design Karnaugh map for P1: Q1 Q2 Q1 Q0

19
Lecture 12CS1Q Computer Systems - Simon Gay 19 PNM Second Design Karnaugh map for P0: Q1 Q2 Q1 Q0

20
Lecture 12CS1Q Computer Systems - Simon Gay 20 PNM Second Design States 110 and 111 are not needed. We would like the counter to advance from state 101 to state 000. This can be achieved by connecting the Reset input to a small circuit which will activate Reset when the state reaches 110. If Reset is active high, then we can use If Reset is active low, then we need

21
Lecture 12CS1Q Computer Systems - Simon Gay 21 PNM Second Design reset circuit Q2Q1Q0 Reset Clock output circuit P0P1P2 Exercise: complete the circuit.

22
Lecture 12CS1Q Computer Systems - Simon Gay 22 Accepting FSM Recall the transition diagram for the FSM which accepts binary sequences of the form 10101… ,1 initialaccepting We’ll use the first design technique from the Prime Number Machine.

23
Lecture 12CS1Q Computer Systems - Simon Gay 23 Accepting FSM There are 3 states so we need 2 bits of state information. We’ll use a 2 bit register with outputs (stored values) Q1,Q0 and inputs D1,D0. There is another input: the current bit from the sequence. Call this I. At each clock cycle, D1,D0 (which will be the next state) are calculated from Q1,Q0 and I. Here is the truth table: Q1Q0ID1D XX XX Exercise: work out formulae for D1,D0 as usual.

24
Lecture 12CS1Q Computer Systems - Simon Gay 24 Accepting FSM Karnaugh map for D1: Q1 II Q0 Q1

25
Lecture 12CS1Q Computer Systems - Simon Gay 25 Accepting FSM Karnaugh map for D0: Q1 II Q0 Q1

26
Lecture 12CS1Q Computer Systems - Simon Gay 26 Accepting FSM The final step is to add an output which will indicate whether or not the FSM is in an accepting state. As the accepting state is state 01, we have Q1Q0 D1D0 ResetClock combinational circuit Accept I

Similar presentations

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google