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Joint Design-Time and Post-Silicon Optimization for Analog Circuits: A Case Study Using High-Speed Transmitter Yiyu Shi, Wei Yao, Lei He, and Sudhakar Pamarti Electrical Engineering Dept., UCLA Speakers: Edward Kao and Scott Fukushima

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Outline Introduction Design-Time Optimization Post-Silicon Tuning and Joint Optimization Optimization Framework Experimental Results Conclusions

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Problem Statement Goal To maximize parametric yield for analog circuits Reasons for Concern Analog circuits are highly sensitive to process variation Process variation causes problems for parametric yield and becomes worse with technology scaling Techniques for maximize parametric yield Design-time optimization Post-silicon tuning

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Existing Work Design-time optimization System-level [Stojanovic:CICC’03] System-level and circuit-level co-design [Sredojevic:ICCAD’08] Device-level Transistor sizing and layout optimization [Pelgrom:JSSC’89] Post-silicon tuning Tunable amplifier [Kaya:TCASII’07] Programmable capacitor array for filter, ADC [Huang:JSSC’01] Transistor finger selection to reduce mismatch [Li:ICCAD’08] A lot more adaptive design for analog/mixed-signal circuit … First yield-driven circuit design technique that considers both post-silicon tuning along with design time optimization

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Adaptive / Tunable Circuits Tunable circuits with negative feedback loop to compensate process variation Traditional corner-based design methodology makes sure the circuit satisfies the design spec in all process corners Circuit tunability does not comes for free Yield-driven optimization is required to prevent over-design

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Joint Design-Time and Post-Silicon Optimization Use high speed link transmitter design as an example Proposed goal Maximize yield Yield is defined by BER Satisfy power and area constraints Optimization framework Build model for analog building blocks from SPICE Include V t variation and consider tuning circuit cost Use SPICE-characterized cells as building units Combine branch-and-bound and gradient-ascent algorithm Effectively find the global optimum solution

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Outline Introduction Design-Time Optimization Post-Silicon Tuning and Joint Optimization Optimization Framework Experimental Results Conclusions

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High-Speed Serial Link Example Consider the transmitter pre-emphasis filter Combats inter-symbol interference (ISI) Plays an important role in system performance Consumes most power at transmitter

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Transmission Environment Channel Attenuation Dispersion Reflection Impedance mismatch Inter-symbol interference Band-limited channel Crosstalk Capacitive or Inductive coupling Other random noises ex: circuit thermal noise

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Transmitter Design Pre-emphasis filter Last stage of the pre-driver Pre-filter the pulse with the inverse of the channel a i : input symbol b i : transmitter output W j : filter coefficient Other stages of the pre-driver Sizing is according to logic effort

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Transmitter Design (cont’d) LMS algorithm is used for optimal filter coefficients given the number of taps n Large transistor parasitic capacitance exists Considered as part of the channel Transistor sizing is done through parallel connected unit cells Unit cells α are pre-characterized through simulation Output swing constraint is applied to make sure correct operation region Get rid of SPICE simulation during optimization

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Performance Metric Transmission ReceptionChannel ModulationDemodulation BER = N e = Number of errors R = Data rate t = Test time Bit Error Rate (BER) Error Vector Magnitude (EVM) 1 2 e I Q Error in the received symbol V2V2 V1V1 e = V1V1 - V2V2 R × t > !!

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Performance Metric (cont’d) The relation between EVM and BER can be obtained through simulation Monotonic Highly correlated EVM can be measured efficiently with far less data a i : input symbol b j : transmitter output p j: : channel response r i : received data M: total number of data < 10 4

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Outline Introduction Design-Time Optimization Post-Silicon Tuning and Joint Optimization Optimization Framework Experimental Results Conclusions

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Process Variation Threshold voltage variation Doping fluctuations Short channel device Channel length variation also causes V th variation Becomes dominant in the next few technology generations Pre-emphasis filter coefficients Implemented as CMOS current sources V th Variation induces drain current mismatch Assume 10% variation in V th 30% variation in power BER varies in several order of magnitude

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Post-Silicon Tuning through DAC Current-division DAC is commonly used to combat process variation Two design parameters LSB size ( ): minimum step during digital-to-analog conversion Resolution ( β ): number of bits used

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Power and Performance Variation (a) Without Tuning(b) With Tuning Both power and performance variations are reduced significantly Given the same design Tuning circuits actually bring extra costs Area Larger parasitic → performance downgrade

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Problem Formulation Where , random variable e

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Outline Introduction Design-Time Optimization Post-Silicon Tuning and Joint Optimization Optimization Framework Experimental Results Conclusions

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Yield vs. Power and Area Significant improvement can be expected Solution space surface is rough and many local maxima exists Discrete problem with non-convex objective and constraints 3000 Monte Carlo runs over different unit cell design α, resolution β, and LSB size

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Basic idea: Partition the solution space by LSB size ( ) and unit cell type ( α ) Develop a bound on the performance Discard (fathom) if bound worse than the current best solution Branch and Bound with Gradient Ascent Method Use gradient ascent method to find the local maxima Sequentially take steps in the direction proportional to the gradient. Bound estimation Remove the area and power constraints Use LMS algorithm to find the optimal coefficients Results in best possible performance

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Outline Introduction Design-Time Optimization Post-Silicon Tuning and Joint Optimization Optimization Framework Experimental Results Conclusions

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BER Distribution Comparison Two extreme cases Without tuning circuit All resources are used for filter design Unavoidable large variation One tap filter All resources are used for DAC Has extreme small variance but suffers severe ISI Manually design Assume LSB size is equal for each tap Good balance between above two extreme cases Our algorithm Provides better solution

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Experiment Results Yield comparison for different constraints area v t variation power Improve the yield by up to 47%

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Outline Introduction Design-Time Optimization Post-Silicon Tuning and Joint Optimization Optimization Framework Experimental Results Conclusions

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Use high speed link transmitter design as an example propose to maximize BER yield subject to power and area constraints. Build model for analog building blocks from SPICE and Include V t variation with the consideration of tuning circuit cost Combine branch-and-bound and gradient-ascent algorithm Effectively find the global optimum Experiments show that, compared to manual design, joint design-time and post-silicon optimization can improve the yield by up to 47% Future work Consider the impact of clock Optimize for the whole system, including receiver and clock circuitry

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Thank you !

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