1. Statistical Critical Path Selection for Timing Validation Kai Yang, Kwang-Ting Cheng, and Li-C Wang Department of Electrical and Computer Engineering University of California, Santa Barbara

2. Outline o Abstract o Background o Motivation o Universal Representative Path Set o Statistical Timing Simulator o UR-Path Construction o Experimental Result o Conclusion and Future Works

3. Outline o Abstract o Background o Motivation o Universal Representative Path Set o Statistical Timing Simulator o UR-Path Construction o Experimental Result o Conclusion and Future Works

4. Abstract Statistical critical path selection for timing validation o Path selection aims at tolerating inaccurate timing models o Develop an efficient statistical timing simulator which can model both intra-die and inter-die process variation o Analyze the timing validation quality using the generated patterns for the selected paths  Previous researches utilize static path analysis

5. Outline o Abstract o Background o Motivation o Universal Representative Path Set o Statistical Timing Simulator o UR-Path Construction o Experimental Result o Conclusion and Future Works

6. Background o Continuous shrinking of device feature size increases the following timing effects:  Process Variation  Power Noise  Crosstalk  Random Defects  Thermal Effects o Modeling Issue  Traditional discrete-value timing models are no longer effective  Statistical timing modeling make more sense in deep sub-micron domain

7. Background – Timing Validation o Verify the design with the timing constraints o Functional pattern v.s. structure-based pattern o Focus on the impact of process variations  No target on spot defects o Structure-based pattern  Critical path selection for timing validation  Test pattern generation for selected path set A B C

8. Outline o Abstract o Background o Motivation o Universal Representative Path Set o Statistical Timing Simulator o UR-Path Construction o Experimental Result o Conclusion and Future Works

9. Motivation o Traditional discrete-value modeling not able to efficiently capture deep sub-micron timing effects o Even with a statistical methodology, an accurate timing model may not be available during the design phase o Even with an accurate timing model, the number of selected critical paths for timing validation may be huge

10. Outline o Abstract o Background o Motivation o Universal Representative Path Set o Statistical Timing Simulator o UR-Path Construction o Experimental Result o Conclusion and Future Works

11. Universal-Representative Path o Definition: Universal-Representative Path Set (UR) If we make sure the delays of these paths are less than a given clock period, then we can guarantee that the worst- case circuit timing is also less than the clock period.

12. Factor Analysis v.s. UR-Path 6 aspects in your questionnaire reduced to 3 factors regression Y=function of (3 factors) Y’=function of (6 variables)  regression Factor Analysis Path Selection Representative paths ATPG Statistical Timing Simulation Statistical Timing Simulation  Identify the underlying structure of data matrix

13. Outline o Abstract o Background o Motivation o Universal Representative Path Set o Statistical Timing Simulator o UR-Path Construction o Experimental Result o Conclusion and Future Works

14. Statistical Timing Simulator - DSIM o Objective: build a flexible, accurate, and efficient timing simulator  Support flexible interface for incorporating different DSM timing effects o Inter-Die Process Variation o Hierarchical Intra-Die Process Variation Modeling o Allow us to study the impact of process variations o software released ! o Download source code at http://cadlab.ece.ucsb.edu

15. Statistical Timing Simulator Delay Random Variables Statistical Delay Library Layout Information Intra-Die Process Variation Profile Statistical Timing Simulator -- DSIM Simulation Patterns Circuit Netlist Sample 1Sample 2Sample K ….. Delay 1Delay 2Delay K

16. Experimental Result and Efficiency Statistical Simulation Efficiency – 100 samples and 1000 random patterns – P4 2GHz Linux workstation

17. Intra-Die Process Variations o Process variation can be divided into two categories  Inter-Die Variation  Intra-Die Variation o Inter-die variation is more likely to be random  Modeled in the statistical delay library  Intra-die variation is spatially correlated which is hard to directly modeled into the delay library  Proximately-close devices may have similar behaviors

18. Hierarchical Intra-Die Process Variation Modeling o Originally developed by David Blaauw’s group on channel- length modeling C 30 C 20 C 10 Layout  Each region is associated with a variation parameter C n  C n characterize the change in standard deviation Proximity-closer devices have a stronger correlations in theirs delay Example

19. Impact of Modeled Intra-Die Process Variation o Layout Information – UCLA Capo o Without real process variation profile, randomly setup C n o For each region, the change of accumulative std in percentage is less or equal to 15% o 3000 critical path delay test patterns with 6 different variation profiles

20. Impact of Modeled Intra-Die Process Variation on pattern selection (cont.) Order all patterns based on the worst-case delay and select the first k patterns. Calculate the pattern coverage

21. Summary of DSIM o Each circuit sample has a different but fixed delay configuration o Given a set of patterns, the simulator performs timing simulation on each circuit sample o For a given clock and for each pattern, the simulator can compute the probability of circuit delay exceeding the clock o Consider the effect of intra-die process variations into timing simulation process clk Primary Output

22. Outline o Abstract o Background o Motivation o Universal Representative Path Set o Statistical Timing Simulator o UR-Path Construction o Experimental Result o Conclusion and Future Works

23. UR-Path Construction o Two-Phase algorithm o Path selection:  Select the superset of path (U-Path) from the whole path space which may affect the critical timing  Timing guard-band based selection method to tolerate inaccurate timing model o Path refinement:  Select the subset of path (UR-Path) from U-Path which can represent the timing behavior of the whole U-Path set

24. Phase-1: Path Selection A B C clk Δ c5315 333 clk- Δ 319 o Goal: o Goal: timing guard-band based method to select the set of path which may affect the critical timing o Construction of U-Path [iccad2002]  Given a clock clk and the threshold value Δ, U-Path includes all paths with non-zero critical probabilities to exceed the specified value clk- Δ.  For a large Δ will produce a large number of paths which will make the path selection very inefficient.  Path Refinement c5315

25. Phase-2: Path Refinement o Goal: Select a small set of path which can represent the timing behavior of U-Path o Timing behavior: the possibility to be longer than the clk Identify the path p has the largest critical probability Remove those samples which p is longer than clk For the remaining circuit samples, select the path with the largest critical probability, estimated based on all remaining samples DSIM circuit sample circuit sample circuit sample circuit sample Sample-based method [iccad2002]

26. Phase-2: Path Refinement After phase-1, we get a set of UR-path but due to the inaccurate timing model, we need to enlarge the path set  Correlation based heuristic – statistical factor analysis  Select the paths which are more independent  Paths with high correlation tend to have similar timing behavior UR-path setRemaining paths sorted with mean delay Pick one path p’ can calculate the correlation coefficient with each path in UR-set If the correlation is less than the given threshold value, include p’ into UR-path set

27. Outline o Abstract o Background o Motivation o Universal Representative Path Set o Statistical Timing Simulator o UR-Path Construction o Experimental Result o Conclusion and Future Works

28. Experimental Setup o Incorporate the statistical simulator to calculate the failing sample rate as the evaluation metric o Perform the proposed path selection with inter- die process variation only  Modeled directly in the statistical delay library o Evaluate the quality of the resulting pattern of the circuit samples with both intra-die and inter- die process variations  To demonstrate the proposed method can tolerate the inaccurate timing model

29. Metric: Failing Sample Rate Circuit Instance with both Inter-die and Intra-die variations Test set T Cause delay Exceeding clock? Not-Detected no Detected Statistical Timing Simulator yes Failing Sample Rate Detected + Not-Detected = Detected

30. Experimental Result o Construct UR-Path set with different correlation coefficient o Compare with other path selection strategies o The number of selected critical path converge quickly compare to the traditional selection methodology Ind32opt

31. Experimental Results c2670opt

32. Outline o Abstract o Background o Motivation o Universal Representative Path Set o Statistical Timing Simulator o UR-Path Construction o Experimental Result o Conclusion and Future Works

33. Conclusions and Future Work o Propose a sample-based strategy to select statistical critical paths for timing validation. Experiment shows that the number of selected path converge quickly. o For some circuits, the proposed sampled-based method is much more efficiency than the traditional critical path selection. o Develop an efficient statistical timing simulator which can simulate both intra-die and inter-die delay. Conclusion Future Work u Theoretically analyze the path selection problem for timing validation u Incorporate real process variation profiles to evaluate the proposed methodology