Presentation is loading. Please wait.

Presentation is loading. Please wait.

Processor Register Set of M16C 2 banks of general-purpose registers 4 16-bit data registers R0 - R3 Upper and lower bytes of registers R0 and R1 can be.

Similar presentations


Presentation on theme: "Processor Register Set of M16C 2 banks of general-purpose registers 4 16-bit data registers R0 - R3 Upper and lower bytes of registers R0 and R1 can be."— Presentation transcript:

1 Processor Register Set of M16C 2 banks of general-purpose registers 4 16-bit data registers R0 - R3 Upper and lower bytes of registers R0 and R1 can be used as 8-bit registers (R0L, R0H, R1L, R1H) 2 16-bit address registers A0 & A1 Can access pairs of registers as 32-bit registers: R2R0, R3R1, A1A0 1 Frame base register R0 R1 R2 R3 A0 A1 FB Data register Address register Frame base register R0 R1 R2 R3 A0 A1 FB User Stack Pointer Interrupt Stack Pointer Static base register Flag register USP ISP SB FLG PC INTB Program Counter Interrupt table register R0H R0L R0H R1L R1H Bank 0 Bank 1 Copyright © 2011 DSR Corporation

2 Bus Slave Selection Port enable (chip select) Only one slave device is active and accepts requests from the bus Decode address: get the most significant bits of the address 2 Memory 1 CPUMemory 1 Memory 2 16-bit Master Slave 0x0000 0x4000 Memory 2 Address Decoder 0x8000 Chip Select EN 01 active EN Memory Map Port enable 0x1000 : x2000 : x4000 : x5000 : Copyright © 2011 DSR Corporation Address signal 00 active The upper 2 bits

3 Peripheral Device: Control Register The control registers are used to set up different modes Some features are configured by separate bits The first step in programming peripheral devices is to understand control registers of the device 3 NameAddress R/W Access Size Timer A0 mode register 0x0396R/W8 Timer A0 register 0x0387R16 Counter start flag 0x0380R8 Example of the configuration register (M16C timer) TMOD0TMOD1MR0MR1 MR2MR3TCK0TCK Timer A0 mode register Specify the operating mode 00: Timer mode 01: Event counter mode 10: One-shot timer mode 11: Pulse with modulation (PWM) mode Counter source select bit Different functions depending on the mode Copyright © 2011 DSR Corporation

4 Peripheral Devices: Using the GPIO as an Output Port Examples of HSB16C (speaker sound generators) 1 LED is connected to port register, lights when 1 is written 4 CPU 0xF000 Address 0x03E0 GPIO … 1 … VCC 1 LED4 : On M16C (microcontroller) 0 1 LED3 : Off Program mov.b #1h, 03e0h 0xF120 PC Write memory instruction Port Registers Memory LED4 lights in C *((char*)0x03E0) = 0x01 Copyright © 2011 DSR Corporation

5 Peripheral Devices: Using the GPIO as an Input Port Examples of HSB16C The value of the port register is 1 when the switch is pressed. 5 CPU 0xF000 Address 0x03E1 GPIO SW9 : On M16C 0 1 SW8 : Off Program mov.b 03e1h, R1 0xF120 PC Read memory instruction Port Registers Memory Check SW9 in C if(*((char*)0x03E1) & 0x20 == 0x20){… } GND VCC Copyright © 2011 DSR Corporation

6 Peripheral Device: Pull-up and Pull-down High and low voltage values (Hi and Lo) are used to determine the 1 and0 digital value Example: When the supply voltage is nearly 5v, 4 ~ 5v is Hi, 0 ~ 1v is Lo Digital signal voltage values must be in the range of Lo or Hi Pull-up and pull-down Circuit configuration for stable electrical input when connecting a switch to an input GPIO port 6 Example of pull-up Switch ONSwitch OFF Copyright © 2011 DSR Corporation Switch Port Register

7 Peripheral Device: Serial I/O Set specific value to control registers to configure I/O port Transmitter side: read value to send from special register, put it to transmit the buffer Often FIFO is used Receiver side: get received byte from buffer and put it to special register To check if send or receive complete, check the status register 7 Shift register FIFO Transmit Buffer Shift register FIFO Receive buffer Control / status register Transmission line CPU Transmitting side Receiver Copyright © 2011 DSR Corporation

8 Programmable Interrupt Controller (PIC) Accept multiple interrupt requests, issue a single interrupt request to a processor Each interrupt request can be configured to be ignored Interrupt Source Register is used to determine what interrupt occurred Several PICs can be used in cascade 8 Interrupt enable/disable Interrupt request 1 Interrupt request 2 Interrupt request 3 Interrupt request 4 Mask register Source Register PIC CPU Get interrupt information Stores information about interrupt Copyright © 2011 DSR Corporation


Download ppt "Processor Register Set of M16C 2 banks of general-purpose registers 4 16-bit data registers R0 - R3 Upper and lower bytes of registers R0 and R1 can be."

Similar presentations


Ads by Google