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Metallization of Submicron Features in High-End Semiconductor Devices by Copper Electroplating Uziel Landau Department of Chemical Engineering Case Western Reserve University Cleveland, OH Presented at ENERGIZER 2/4/05

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High-Tech: CVD, PVD deposition of semiconductors Drugs development CatalysisLow-Tech: Oil refining Electrical machinery Steel manufacturing Underlying science is well-established: Electroplating (some aspects) Technology precedes the science – empiricism

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Outline Overview of Copper Interconnect Metallization Rationale for this work Analyzing the additives effects* Experimental Investigations Modeling of Additives Transport + Adsorption Simulation of the via-fill process Scaling Issues & Wafer-scale Conclusions

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Recent Microprocessors 70 Million transistors/processor ~ 70 Million transistors/processor ~ 300 Million interconnects/processor ~ 200 Processors/200 mm wafer Metallized Wafer

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To reduce t - Lower resistivity (ρ) Lower dielectric constant (K) t = R C Device Speed vs. Size Time Constant Interconnect resistance R Smaller line size Longer Time delay GATE INTERCONNECT DEVICE GATE VIA TRENCH r SiO 2 Al2.65 μΩ cm Cu1.68 μΩ cm Ag1.59 μΩ cm J. Dahm and K. Monnig, Sematech, AMC 1998 Conf. Proceedings, pp smaller

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Interconnect Cross-section Moving from Al to Cu Interconnects Al InterconnectsCu Interconnects Transistor Gate

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Copper Interconnect Metallization Etch Via SiN Etch stop Insulator (SiO 2 ) Routes for copper metallization: PVD ( /min) CVD (0.2 /min) Electroless plating (0.2 /min) Electroplating (1 /min) DUAL DAMSCENE Etch Trench PVD barrier Copper seed Electrodeposited copper After CMP Introduced by IBM (Andricacos, Uzoh, Dukovic, Horkans, Deligianni)

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Advantages of Copper Metallization Higher conductivity Reduced time delay Higher current density at lower power Scalability – finer lines at lower levels Improved EM performance Fewer steps – Dual Damascene Process Fewer defects Less equipment, space Lower cost Faster processing Less costly equipment Environmentally benign Introduced by IBM (Andricacos, Uzoh, Dukovic, Horkans, Deligianni) Introduced by IBM (Andricacos, Uzoh, Dukovic, Horkans, Deligianni) Commercially implemented ( IBM, Intel, Motorola/AMD, TI,…) Commercially implemented ( IBM, Intel, Motorola/AMD, TI,…)

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Issues in Copper Metallization Attitude- Extending wet chemistry to dry semiconductor processing Extending wet chemistry to dry semiconductor processing Doubting the ability of plating to meet the challenge Doubting the ability of plating to meet the challenge Meeting unparalleled requirements of purity and precision Meeting unparalleled requirements of purity and precisionTechnical- Via scale: Via scale: Bottom up fill Bottom up fill Seed layer in aggressive geometries (<0.2 μm) – continuity Seed layer in aggressive geometries (<0.2 μm) – continuity Wafer scale: Wafer scale: Thickness uniformity of the copper over-plate Thickness uniformity of the copper over-plate Resistive substrate (~1000 A seed) Resistive substrate (~1000 A seed) Modeling and scaling (300 mm, current density, flow…) Modeling and scaling (300 mm, current density, flow…) Process Integration Process Integration

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Contact ring Plating cell

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- + - Cell-Design © simulation. 500Å Cu seed ( 0.34 /cm) i ~ 50 mA/cm 2 ( mA/cm 2 ) S/cm Resistive substrate: Practical complications Flow: Entrance and exit Additives distribution Kinetics Power Wafer - Scale Issues - + perfect cylinder Ideal –

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Equivalent resistive network - vvvvv V R electrolyte + vvvvv V I edge I center R seed R electrolyte vvvvv V V applied = V + - V - = = I center R electr. + I seed R seed. = I edge R electr. I edge I center A high resistivity electrolyte will minimize the resistive seed effect R seed

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Typical acid concentration: M Role of acid: provide conductivity Removing the acid; cm M CuSO M H 2 SO 4 Cu ++ : z C = 0.25x10 -3 M/cm 3 Cu ++ = cm -1 SO 4 --: z C = 0.25x10 -3 M/cm 3 SO4 -- = cm -1 z C = 1.8 x10 -3 M/cm 3 H + = cm -1 HSO 4 -: z C = 1.8x10 -3 M/cm 3 SO4 - = 0.09 cm -1 Total = cm -1 Low-acid electrolyte

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Electric Contact SEEDED WAFER Final Copper Profile 1.8 M H 2 SO 4 C L 20s 40s 60s 80s 100s PLATED COPPER SEEDED WAFER No Acid Final Copper Profile 20s 40s 60s 80s 100s C L Electric Contact PLATED COPPER 1.8 M Sulfuric AcidNo Added Acid Effect of Electrolyte Conductivity Cell-Design © simulationsCell-Design © simulations Thickness ratio = 1.4 Thickness ratio = 1.1 i avg ~ 35 mA/cm 2

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Flow Simulations 60 RPM + 4 GPM Impinging Flow Wafer Scale Cell-Design Simulations

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Flow Simulations Micro-Scale Transport within the via is due to diffusion Cell-Design Simulations

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Flow - reduce (but inside via only diffusion pertains...) Raise copper conc.: M 0.85M (solubility issue -- reducing acid is helpful - common ion effect t (transport number): Enhancing mass transport

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–No or low acid counteracts the resistive seed effectcounteracts the resistive seed effect supports higher copper solubilitysupports higher copper solubility chemical enhancement of transportchemical enhancement of transport environmental, safety and handling benefitsenvironmental, safety and handling benefits less corrosiveless corrosive enhances copper seed stability in the presence of dissolved oxygenenhances copper seed stability in the presence of dissolved oxygen –High copper concentration enhances transportenhances transport New electrolyte formulation 1~2 M (pH=0) ~ 0.1 M (pH = 1~3.5) M M

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< 50 Sec 2-3 Min Rapid Fill of Vias and Trenches

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Gap-Fill Modes Bottom-up Fill (Good!) Void Conventional Plating (unacceptable) Seam Conformal Plating ( unacceptable)

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Via-fill modes Conventional Plating Conformal Plating Bottom-up Plating VOID SEAM

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BOTTOM-UP plating of vias Issues in Copper Metallization VOIDSEAMBottom-up Special mixture of plating additives can lead to bottom-up fill. However, additives selection is empirical and fundamental information about their role is lacking.

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Special plating chemistry required for bottom-up fill. What promotes Bottom-up Fill ? INHIBITOR Polyether (PEG) INHIBITOR ~100 – 400 ppm ACCELERATOR Bis(3-sulfopropyl) disulfide (SPS) ACCELERATOR ~20 – 50 ppm 2-imidazolidinethione ~2 – 5 ppm PLATING CHEMISTRY: ~ 0.5 M CuSO 4 + H 2 SO ppm Cl - + H-(OCH 2 CH 2 ) n -OH

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Variable Adsorption leads to Variable Kinetics and to Bottom-up fill: Suppressor, e.g. PEG Slow deposition Fast deposition Enhancer, e.g. Organic di-sulfide

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Variable Deposition Rates Due to Non-uniform Inhibition i [mA/cm 2 ] V Polarization Curves Enhanced Kinetics (via) Suppressed Kinetics (flat wafer) mV 100

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Key Issues in Bottom-up Plating All metallization chemistries contain : PEG (inhibitor / suppressor) SPS (accelerator / anti-suppressor) Chloride ions WHY ONLY THESE and NOT OTHERS ??? PEG SPS Cl - ++=GOOD SPS Cl - +=BAD = PEG + SPS =BAD PEG + Cl -

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Key Issues Accelerated bottom growth should terminate before top surface is approached Accelerated bottom growth should terminate before top surface is approached Top surface must remain passivated for only a limited time Top surface must remain passivated for only a limited time Only negligible amount of additives incorporates in the deposit or decomposes: steady-state models inadequate Only negligible amount of additives incorporates in the deposit or decomposes: steady-state models inadequate Via fills in s. – Transient interactions are crucial Via fills in s. – Transient interactions are crucial Understanding of transient additives transport, adsorption, and interactions.

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A Few Proposed Mechanisms West et al. Diffusion Controlled Additives Transport Unaddressed Issues: Additives interactions Unsteady state effects Moffat et al. Curvature Enhanced Accelerator Coverage Unaddressed Issues: Unsteady state effects Role of PEG Arbitrary initial conditions Limitations: Steady state model Many arbitrary adjustable parameters. IBMs model Adjustable Kinetics along the Via Walls

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Objectives Characterize the transient additives interactions Characterize the transient additives interactions Explain and model the bottom-up fill process Explain and model the bottom-up fill process Develop a Simulation for the Bottom-Up Fill Develop a Simulation for the Bottom-Up Fill Should correlate experimental observations Should correlate experimental observations Without adjustable parameters or extreme assumptions Without adjustable parameters or extreme assumptions S S P P time ?

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Experimental Setup Plating Conditions: Electrolyte : 0.5 M CuSO 4 + H 2 SO 4 (pH~2) Galvanostatic : i = 30 mA/cm 2 Rotation speed : 200 rpm Additives: Chloride ions : ppm Polyethylene glycol (PEG) : ppm Bis (3-sulfopropyl)-disodium sulfonate (SPS) : ppm RDE Cu/CuSO 4 Reference Syringe Additives Copper plating chemistry

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PEG Adsorption – Effect of Cl - Overpotential (mV) Time t (s) Injection time Only PEG Only Cl - PEG + Cl - No additive Cl - essential for PEG assisted polarization

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PEG Adsorption Overpotential (mV) Time t (s) Injection time 50 ppm PEG 100 ppm PEG 200 ppm PEG t ~ L 2 /D ~ 7 s PEG saturation at 200 ppm Cl - Effect of Concentration

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SPS Adsorption on Clean Electrode Overpotential (mV) Time t (s) Injection time 50 ppm SPS + 70 ppm Cl - FAST ADSORPTION KINETICS Clean Electrode

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SPS Adsorption on PEG-covered Electrode Overpotential (mV) Time t (s) Injection time 50 ppm SPS SLOW depolarization of the electrode* t ~ 100 s PEG saturated electrode (+ chloride) 20 ppm SPS * R. Akolkar and U. Landau, AIChE Proceedings (2003).

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Competitive Adsorption (SPS+PEG) Overpotential (mV) Time t (s) Injection time FAST polarization by PEG SLOW depolarization by SPS due to displacement of PEG Interactions dominant during the via-fill period (~20-50 s)

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Competitive Adsorption (SPS+PEG) Current Density (mA/cm 2 ) Overpotential (mV) SPS accelerated kinetics PEG inhibited kinetics (short time) Slow depolarization by SPS t=10st=50s t=0s Disc rotation = 50 rpm Time

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Time Scales for Transport, Adsorption and Interaction PEGSPS Transport SLOW (D~10 -6 cm 2 /s) FAST (D~10 -5 cm 2 /s) Adsorption on clean electrode VERY FASTFAST (t~5 s) Interaction Cannot displace SPS Displaces PEG slowly (t~100 s) V t (s) PEG + Cl - V t (s) 20 ppm SPS

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Via-Fill Model: Initial Surface Coverage Capillary Flow ADSORPTION on clean surface - PEG adsorbs rapidly SPS adsorbs slower than PEG SPS PEG Consequently - All PEG (~100 molecules) adsorbs SPS starts adsorbing on PEG-free area PEG Concentration Gradient Develops Low V/A High V/A

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Via-Fill Model: PEG Transport Delay PEG surface coverage Normalized Depth z* t=6s t=1st=3s t=8s TOP BOTTOM PEG diffuses slowly + Adsorbs on sidewalls PEG reaches via bottom after ~10 s SPS ADSORBS RAPIDLY ON PEG- FREE VIA BOTTOM *Via is 0.1 μ dia., 1 μ deep

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Via-Fill Model: PEG Transport Delay MORE SPS Coverage MORE PEG Coverage Accelerated Bottom-up Growth *R. Akolkar and U. Landau, J. Electrochem. Soc., 151 (11) C702 (2004)

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Modeling of Via Fill 1 μ 0.1 μ I I II Via Exterior ( I )Via Interior ( II ) Solve for C ( z, t ) and θ ( z, t ) in I and II Time Dependent Transport Kinetics (TTK) Approach Wafer Surface BULK Electrolyte VIA TOP VIA BOTTOM

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Modeling of Via Fill – TTK Approach WAFER TOP SURFACE Adsorption = k ( 1 – θ ) 60 μ Diffusion boundary layer NO CONVECTION BULK PEG Additives Transport to the WAFER TOP SURFACE small features are neglected Concentration Profile given by :

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Via Exterior: Flat wafer surface PEG inhibits flat wafer surface instantaneously ( t ~ 3-4 s) PEG surface coverage Time t (s)

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Diffusion IN OUT Adsorption on the sidewalls Additives Transient Processes INSIDE THE VIA Additives Transport (PEG diffusion) Adsorption on sidewalls (Kinetics) Additives Interactions (SPS displaces PEG) Modeling of Via Fill* R = 0.1 μ L = 1 μ *R. Akolkar and U. Landau, Abstract No. 157-E1, 205th ECS Meeting, San Antonio (2004). Model incorporates (NO Adjustable Parameters):

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Modeling of Via Fill – TTK Approach Transport and Competitive Adsorption of both PEG & SPS PEG Adsorption : N i,T N i,T =0 N i,A N i,D z z+ z z=0z=L Diffusion IN OUT SPS Adsorption : PEG Displacement: SPS Intreractive Adsorption :

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Diffusion IN OUT Adsorption Additives Transient Processes INSIDE THE VIA Modeling of Via Fill* R = 0.1 μ L = 1 μ *R. Akolkar and U. Landau, Abstract No. 157-E1, 205th ECS Meeting, San Antonio (2004). PEG Transport PEG Coverage SPS Coverage DIFFUSION ADSORPTION PEG-SPS INTERACT

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Additives-Assisted Deposition Kinetics Modulated current density COPPER SURFACE Cu ++ SPS PEG

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Additives-Assisted Deposition Kinetics Total current density : COPPER SURFACE Cu ++ SPS PEG Deposit thickness:

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PEG-1s SPS-1s PEG Surface Coverage SPS Surface Coverage Distance Into the Via VIA TOP VIA BOTTOM TRANSPORT- ADSORPTION PROCESS (0 < t < 5 s) ADDITIVES COVERAGE AT SHORT TIMES SHORT TIMES PEG SPS High PEG Low SPS Low PEG High SPS

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PEG-3s SPS-3s PEG Surface Coverage SPS Surface Coverage Distance Into the Via VIA TOP VIA BOTTOM TRANSPORT- ADSORPTION PROCESS (0 < t < 5 s) ADDITIVES COVERAGE AT SHORT TIMES SHORT TIMES

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PEG-5s SPS-5s PEG Surface Coverage SPS Surface Coverage Distance Into the Via VIA TOP VIA BOTTOM TRANSPORT- ADSORPTION PROCESS (0 < t < 5 s) ADDITIVES COVERAGE AT SHORT TIMES SHORT TIMES

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PEG-1s PEG-3s PEG-5s SPS-5s PEG Surface Coverage SPS Surface Coverage Distance Into the Via VIA TOP VIA BOTTOM TRANSPORT- KINETICS REGIME (0 < t < 5 s) ADDITIVES COVERAGE AT SHORT TIMES

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PEG COVERAGE AT LONG TIMES PEG Surface Coverage Distance Into the Via, z* VIA TOP VIA BOTTOM PEG displacement by the SPS (t~100 s) INTERACTION REGIME (5 < t < 100 s) 10 s 30 s40 s time

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SPS COVERAGE AT LONG TIMES SPS Surface Coverage Distance Into the Via, z* VIA TOP VIA BOTTOM SPS displaces the adsorbed PEG (t~100 s) INTERACTION REGIME (5 < t < 100 s) 30 s 20 s 10 s time

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SPS Surface Coverage Time (s) VIA TOP VIA BOTTOM INTERACTIONS TRANSPORT-KINETICS SPS adsorbs on PEG-free bottom SPS adsorbs on PEG- covered bottom SPS - Comparison: Via Top vs. Via Bottom

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PEG Surface Coverage Time (s) VIA TOP VIA BOTTOM PEG - Comparison: Via Top vs. Via Bottom INTERACTIONS TRANSPORT-KINETICS PEG diffuses to the via bottom SPS displaces the adsorbed PEG

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Slow PEG transport allows SPS time to adsorb Effect of PEG Transport Delay Flow affects PEG transport only Kinetic Resistance (ohm) Time t (s) Simulated via bottom (i=30 mA/cm 2, 90rpm) Simulated via top (i=15 mA/cm 2, 200rpm) Injection time Flat RDE used to simulate transport to the via

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PEG Surface Coverage Time (s) VIA TOP VIA BOTTOM COMPARISON: Via Top vs. Via Bottom PEG diffuses to the via bottom SPS displaces the adsorbed PEG *R. Akolkar and U. Landau, J. Electrochem. Soc., submitted. LONG TIMES Kinetic Resistance Time (s) Corresponds to via top RDE Experiments Corresponds to via bottom

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Effect of varying surface area on additives coverage Surface area at via bottom shrinks PEG bonds weakly and re-equilibrates with the electrolyte SPS bonds strongly and does not leave surface SPS (or PEG) do not incorporate appreciably within the deposit Material balance on SPS:

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SPS Surface Coverage on the via bottom Time (s) SPS Coverage from transport modeling + Area Reduction Effects SPS Coverage predicted by Transport-Kinetics model alone SURFACE AREA REDUCTION effects SPS saturation at the bottom A. C. West, S. Mayer and J. Reid, Electrochem. Solid-State Lett., 4 (7), C50 (2001). T. P. Moffat et al., Electrochem. Solid-State Lett., 4 (4), C26 (2001).

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PEG Surface Coverage on the via bottom Time (s) EFFECT OF LOCAL AREA REDUCTION PEG Coverage accounting for the Local Area Reduction PEG Coverage predicted by Transport-Kinetics approach alone Complete Removal of the PEG

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Modeling the Bottom-up Fill* t = 0 s Uniform additives composition everywhere PEG SPS * R. Akolkar and U. Landau, J. Electrochem. Soc., accepted for publication.

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t 0 + s Fast inhibition on the flat wafer Fast adsorption of PEG on via sidewalls PEG SPS Modeling the Bottom-up Fill

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t = 1-2 s Inhibited wafer surface Fast transport of PEG to upper via sidewalls PEG SPS Fast diffusion and adsorption of SPS on bare copper Modeling the Bottom-up Fill SPS diffuses fast – 20 times faster than PEG

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t ~ 10 s Inhibited wafer surface and via sidewalls PEG SPS PEG cannot polarize SPS covered surface Modeling the Bottom-up Fill

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t ~ 50 s SPS slowly depolarizes the wafer surface by displacing PEG PEG SPS Modeling the Bottom-up Fill

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No additives initially inside the via due to the low volume/area ratio. High volume/area ratio on the wafer top surface leads to instantaneous inhibition by PEG. Slow transport of diffusion limited PEG to the via bottom ( t ~ 8-10 s ). The PEG transport delay allows time for fast diffusing SPS to adsorb on the via bottom. Delayed arrival of PEG cannot displace the stronger adsorbing SPS. Summary of Key Aspects of Bottom-up Fill

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Scaling Analysis of Additives Transport No PEG inside the via at t 0 due to small V/A ratio PEG is transported by diffusion from the bulk into the via Why is a via with reactive sidewalls associated with a large PEG transport delay ? Time constant t ~ L 2 /D For a 1 μ via, the time constant t ~ 0.02 s

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PEG Transport Delay PEG surface coverage at via bottom Time (s) Non-reactive Sidewalls Reactive Sidewalls PEG transport delay: no PEG at via bottom for ~8 s Numerical Simulation of PEG Transport

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Scaling Analysis Transport-Adsorption Model : Adsorption Rate Diffusion Rate k, μ depends on time – Short times – Low θ – High k, μ Long times – High θ – Low k, μ μ decreases with time where : Thiele Modulus L 2R One-dimensional Pseudo Steady-State Model Infinite Sink at Via Bottom Uniform inhibition on the sidewalls

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One-dimensional Transport Kinetics Model PEG Concentration, C* Normalized Depth, z* Decreasing μ due to gradual inhibition of sidewalls μ = 30 μ = 1 Via TopVia Bottom Concentration Profiles No Transport of PEG to the Bottom at high μs Scaling Approach

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Establishing Relationship Between k and t Amount of PEG Entering the Via Amount of PEG Adsorbed on the Sidewalls In time t : =+ Amount of PEG Accumulated in the via Assumptions : Negligible PEG Accumulation Average Diffusion Flux In : Linear Time Dependence of k :

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PEG Transport Delay Normalized Flux of PEG at the via bottom Time t (s) Uninhibited via sidewalls θ side = 0 Inhibited via sidewalls and bottom θ ~ 1 PEG transport delay: no PEG at via bottom for ~9 s Scaling Approach

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PEG Transport Delay Effect of Via Radius (L=1 μm) PEG Transport Delay (s) Via Radius (μm) High Aspect Ratio Vias Low Aspect Ratio Vias INTEL 90nm technology Inverse dependence of PEG transport delay on via radius Transients due to Transport Kinetics significant for high aspect ratios

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PEG Transport in Vias with Sloping Sidewalls How does the via geometry affect the PEG transport characteristic ? Ф Ф Ф = positive (Outward Sloping) RE-ENTRANT Ф = 0 (Non-Sloping) Ф = negative (Inward Sloping) 2R o

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One-dimensional Unsteady-State Model Transport Model for a Via with Sloping Reactive Sidewalls : Diffusional Flux IN OUT Adsorption Ф > 0Ф < 0 Diffusion IN = Diffusion OUT + Adsorption + Accumulation Diffusion = Adsorption = Effect of varying radius stronger on transport

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One-dimensional Unsteady-state Model Surface Coverage at the via bottom (θ PEG ) Time t (s) SLOWER Transport FASTER Transport Ф = -1.1 o Ф = 0 o Ф = 10 o

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Quantitative Modeling of Via-Fill Time Scales t 10 st > 10 s Transport-kinetics time scale Additives Interaction time scale SHORTLONG PEG SPS

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Transport Kinetics Time Scale PEG SPS Generation of differential plating kinetics between the via top and bottom – initiation of superfill. Copper deposition preferentially occurs at the via bottom. t 10 s SHORT

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additives distributionRequires additives distribution kineticsEffect of additives surface coverage on the kinetics NUMERICAL APPROACHNUMERICAL APPROACH Solution of the Nernst-Planck Equations or a simplified case (Laplaces Equation) Time stepping moving boundary SEMI-QUANTITATIVE APPROACHSEMI-QUANTITATIVE APPROACH Neglect concentration variations inside the via Move electrode boundaries on the basis of local kinetics using Faradays law Simulation of Via-Fill

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Simulation of Deposit Propagation Variable kinetics + Moving boundaries 2 =0 2 C =0 i = f ( η) Passivated kinetics (PEG->SPS) Accelerated kinetics (SPS) Variable kinetics [Partially passivated, f(t)] Virtual electrode; Outer edge of diffusion layer C

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Numerical Simulation of Via-Fill – Variable Kinetics* * U. Landau, E. Malyshev, R. Akolkar and S. Chivilikhin, AIChE Proceedings (2003). Cell-Design Simulations MOVING BOUNDARIES Fill Time: 48 sec. Overpotential: mV Bottom: i = 60 mA/cm 2 Top: i = 0.24 mA/cm mA/cm 2 (Depolarization by SPS) Sidewalls: Interpolated kinetics between Top and Bottom SiO 2 Electrolyte SiO 2 Electrolyte

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SiO 2 Electrolyte Seam Cell-Design Simulations Via Fill Simulation Plating Time: ~147 sec. Overpotential: - 80 mV Bottom: i = 10 mA/cm 2 i 0 = 1.12 mA/cm 2 C = 0.83 Top: i = 0.05 mA/cm mA/cm 2 High Depolarization by SPS: i 0 = 3.1 μA/cm mA/cm 2 C = 0.9 Sidewalls: Interpolated kinetics between Top and Bottom Current density has been lowered: No Bottom-Up Fill No Bottom-Up Fill 1 sec time intervals

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z* r* 10 s 20 s 30 s 35 s Flat Bottom- up Growth i avg =63 mA/cm 2 SIMULATIONS OF THE VIA-FILL η = 120 mV PEG = 100 ppm SPS = 20 ppm VIA-FILL *V. Dubin, Microelectronic Engineering, 70, 461, 2003.

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z* r* Seam after 900 s Conformal Deposition η = 120 mV PEG = 100 ppm SPS = 0 ppm VIA-FILL SIMULATIONS: Effect of SPS η = 120 mV PEG = 100 ppm SPS = 100 ppm z* r* 15 s Rapid depolarization on the via sidewalls Center- line Voids

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Growth Profile at Low overpotential z* r* Seam after 75 s Low bottom-up current density i ~ 12 mA/cm 2 η = 80 mV PEG = 100 ppm SPS = 20 ppm Bottom cannot escape depolarizing sidewalls GOOD BAD

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Modeling of Superfill – Effect of Current Density C peg =200 ppm C sps =20 ppm Via AR = 10 V = 130 mVV = 60 mV Bottom-up growth Seam at the mouth due to depolarizat ion by SPS 30 s 200 s 1 mA/cm 2 21 mA/cm 2

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Wafer-scale Modeling Rationale for study Only wafer-scale parameters, e.g., total current (I) or voltage (V) are measurable current/ potentialwaveformsOptimize the process by identifying current/ potential waveforms Transient nature of wafer-scale processes due to: Transient additives interactions Geometry changes during via-fill

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Wafer-scale Modeling 300 mm wafer 0.2 μ dia., 1 μ deep vias (via loading ~ 6 %) Empirical observations during wafer metallization: Current is initiated upon wafer immersion Initial overall current is low Current is increased as via-fill is initiated

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Wafer-scale Modeling Current balance on the entire wafer : Assuming inhibited sidewall kinetics similar to the wafer top The wafer geometric current density :

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Wafer Current Density, mA/cm 2 Time, s Wafer-scale current transients Rapid wafer depolarization at short times (t < 10 s) Wafer current drops at long times (t>25s) SPS = 20 ppm PEG = 100 ppm Wafer Current, A η = 0.12 V (constant Driving force)

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Wafer Current Density, mA/cm 2 Time, s Comparison with Experiments Model predictions in agreement with experiments * Experimental data: J. Reid et al., Electrochem. Solid-State Lett., 6(2) C26 (2003). Source: J. Reid et. al.*

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Wafer Current Density, mA/cm 2 Time, s Wafer-scale i vs. t : Effect of potential η = 0.12 V VIA-FILL COMPLETION SPS = 20 ppm PEG = 100 ppm Via loading = 6.3% η = 0.13 V

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Wafer Current Density, mA/cm 2 Time, s Wafer-scale i vs. t : Effect of SPS conc. SPS = 20 ppmDefect-free Fill η = 0.12 V PEG = 100 ppm Via loading = 6.3% SPS = 30 ppm Centerline Voids

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Wafer Current Density, mA/cm 2 Time, s Wafer-scale i vs. t : Effect of via loading Via loading = 6.3% η = 0.12 V PEG = 100 ppm SPS = 20 ppm Via loading = 12.6%

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Wafer Voltage (mV ) Voltage Implication of Constant Current Time, s Wafer Current Density, mA/cm 2 Time, s SPS =` 20 ppm PEG = 100 ppm η = 0.12 V (constant Driving force) Current 120 Too high – bottom defects Too low– centerline defects

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A comprehensive model for the bottom-up fill is presented. WITHOUT invoking any adjustable parameters Based on experimentally characterized additives effects The model explains: Specific role of the PEG and SPS in the multi- component additives system The effect of operating parameters and via geometry Wafer-scale current response. Major Conclusions

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Acknowledgements: Case Prime Fellowship to Rohan Akolkar General Motors Research and Development The Dept. of Chemical Engineering, CWRU John DUrso David Rear Mark Bubnick Applied Materials Yezdi Dordi Peter Hey THANK YOU ALL! Dr. Rohan Akolkar

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Additives Distribution during TK time scale PEG Surface Coverage Normalized depth, z* SPS Surface Coverage Via TopVia Bottom No PEG or SPS on the via sidewalls at t = 0 t = 0 s

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Additives Distribution during TK time scale PEG Surface Coverage Normalized depth, z* SPS Surface Coverage Via TopVia Bottom Inhibited Via Top PEG-free bottom with some SPS t < 1 s

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Additives Distribution during TK time scale PEG Surface Coverage Normalized depth, z* SPS Surface Coverage Via TopVia Bottom Inhibited Via Top Accelerated Via Bottom t ~ 4 s

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PEG Surface Coverage Normalized depth, z* SPS Surface Coverage Via TopVia Bottom High PEG Low SPS Low PEG High SPS t ~ 8 s Additives Distribution during TK time scale

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