1. Metallization of Submicron Features Case Western Reserve Universityin
High-End Semiconductor Devices by Copper Electroplating
Uziel Landau
Department of Chemical Engineering
Case Western Reserve University
Cleveland, OH 44106
Presented at ENERGIZER 2/4/05

2. High-Tech: Low-Tech: Technology precedes the science – empiricism
CVD, PVD deposition of semiconductors
Drugs development
Catalysis
Technology precedes the science – empiricism
Electroplating (some aspects)
Low-Tech:
Oil refining
Electrical machinery
Steel manufacturing
Underlying science is well-established:

3. Outline Overview of Copper Interconnect Metallization
Rationale for this work
Analyzing the additives effects*
Experimental Investigations
Modeling of Additives Transport + Adsorption
Simulation of the via-fill process
Scaling Issues & Wafer-scale
Conclusions

5. Recent Microprocessors
~ 70 Million transistors/processor
~ 300 Million interconnects/processor
~ 200 Processors/200 mm wafer
Metallized Wafer

6. J. Dahm and K. Monnig, Sematech, AMC 1998 Conf. Proceedings, pp. 3-15.
Device Speed vs. Size
TRENCH
Al 2.65 μΩ cm
Cu 1.68 μΩ cm
Ag 1.59 μΩ cm
VIA r
SiO2
GATE
DEVICE
Time Constant
t = R C
Longer Time delay
Interconnect resistance R
smaller
GATE
To reduce t -
Lower resistivity (ρ)
Lower dielectric constant (K)
INTERCONNECT
Smaller line size
J. Dahm and K. Monnig, Sematech, AMC 1998 Conf. Proceedings, pp

7. Interconnect Cross-section
Moving from Al to Cu Interconnects
Al Interconnects
Cu Interconnects
Transistor ‘Gate’

8. Electrodeposited copper
Copper Interconnect Metallization
‘DUAL DAMSCENE’
Routes for copper metallization:
PVD ( m/min)
CVD (0.2 m/min)
Electroless plating (0.2 m/min)
Electroplating (1 m/min)
Etch Via
SiN Etch stop
Insulator (SiO2)
Etch Trench
Electrodeposited copper
After CMP
PVD barrier
Copper seed
Introduced by IBM (Andricacos, Uzoh, Dukovic, Horkans, Deligianni)

9. Advantages of Copper Metallization
Higher conductivity
Reduced time delay
Higher current density at lower power
Scalability – finer lines at lower levels
Improved EM performance
Fewer steps – Dual Damascene Process
Fewer defects
Less equipment, space
Lower cost
Faster processing
Less costly equipment
Environmentally benign
Introduced by IBM (Andricacos, Uzoh, Dukovic, Horkans, Deligianni)
Commercially implemented (IBM, Intel, Motorola/AMD, TI,…)

10. Issues in Copper Metallization
‘Attitude’-
Extending ‘wet chemistry’ to ‘dry’ semiconductor processing
Doubting the ability of plating to meet the challenge
Meeting unparalleled requirements of purity and precision
Technical-
Via scale:
‘Bottom up’ fill
Seed layer in aggressive geometries (<0.2 μm) – continuity
Wafer scale:
Thickness uniformity of the copper over-plate
Resistive substrate (~1000 A seed)
Modeling and scaling (300 mm, current density, flow…)
Process Integration

12. Contact ring
Plating cell

13. Wafer - Scale Issues - - + + Ideal – Resistive substrate:
Cell-Design© simulation.
500Å Cu seed
( 0.34 /cm)
i ~ 50 mA/cm2
( mA/cm2)
k = 0.55 S/cm
Resistive substrate:
Practical complications - +
perfect cylinder
Ideal –
Flow:
Entrance and exit
Additives distribution
Kinetics
Power
Demonstrate cylindrical shape, shields, with cell-design simulations

14. Equivalent resistive network
Rseed
Iedge
Icenter
Rseed
Relectrolyte
vvvvvV
Vapplied= V+- V- =
= Icenter Relectr.+ Iseed Rseed.
= Iedge Relectr. -
vvvvvV
vvvvvV
vvvvvV
vvvvvV
vvvvvV
vvvvvV
vvvvvV
Iedge
vvvvvV
vvvvvV
vvvvvV
vvvvvV
Icenter
Relectrolyte
vvvvvV
vvvvvV
vvvvvV
Refer to previous work: Tobias, Alkire, Landau
Selected results: Phi, Lanzi’s
Modified Phi (?), modified Lanzi’s definition
vvvvvV
vvvvvV
vvvvvV
vvvvvV +
A high resistivity electrolyte will minimize the resistive seed effect

15. Low-acid electrolyte Removing the acid; k : 0.5 0.05 W-1cm-1
Typical acid concentration: M
Role of acid: provide conductivity
Removing the acid; k : W-1cm-1
0.25M CuSO M H2SO4
Cu++: l = z = C = 0.25x10-3 M/cm3 kCu++ = W-1cm-1
SO4--: l = z = C = 0.25x10-3 M/cm kSO4-- = W-1cm-1
H+ : l = z = C = 1.8 x10-3 M/cm kH = W-1cm-1
HSO4-: l = z = C = 1.8x10-3 M/cm kHSO4-= 0.09 W-1cm-1
kTotal = W-1cm-1

16. Effect of Electrolyte Conductivity
iavg~ 35 mA/cm2
SEEDED WAFER
No Acid
Final Copper Profile
20s
40s
60s
80s
100s C L
Electric Contact
Electric Contact
SEEDED WAFER
Final Copper Profile
1.8 M H2SO4 C L
20s
40s
60s
80s
100s
PLATED
COPPER
PLATED
COPPER
Fig. 1: Computer simulations (CELL-DESIGN©) of copper deposition on a resistive wafer. An axi-symmetric cross section through one half of a 200 mm wafer is shown with center of the wafer on the left and electrical contact (wafer circumference) on the right. The vertical axis is magnified to make the copper profile visible. Copper kinetics (i0= 1 mA/cm2, C=0.5, A=1.5) were assumed. Current density was maintained at ~ 35 mA/cm2. 5 growth steps, 20 sec. each were simulated. (a) electrolyte: 0.24 M CuSO M H2SO4. Min. copper thickness = 1.08 ; max. thickness =  (b) electrolyte: 0.85 M CuSO4. Min. thickness = 1.28 ; max. thickness = . No edge exclusion was assumed.
Seed thickness ?
Cell-Design simulations (emphasize that this is a ‘growth’ model’)
Effect of :
conductivity,
seed thickness
diameter
current density
1.8 M Sulfuric Acid
No Added Acid
Thickness ratio = 1.4
Thickness ratio = 1.1
‘Cell-Design’ © simulations

17. Flow Simulations Wafer Scale 60 RPM + 4 GPM Impinging Flow
‘Cell-Design’ Simulations

18. Flow Simulations Micro-Scale
Transport within the via is due to diffusion
‘Cell-Design’ Simulations

19. Enhancing mass transport
Flow - reduce d
(but inside via only diffusion pertains...)
Raise copper conc.: M M (solubility issue -- reducing acid is helpful -common ion effect
t (transport number):

20. New electrolyte formulation
No or low acid
counteracts the resistive seed effect
supports higher copper solubility
‘chemical’ enhancement of transport
environmental, safety and handling benefits
less corrosive
enhances copper seed stability in the presence of dissolved oxygen
High copper concentration
enhances transport
1~2 M (pH=0) ~ 0.1 M (pH = 1~3.5)
M M

21. Rapid Fill of Vias and Trenches
2-3 Min
< 50 Sec

22.    Gap-Fill Modes Seam Void Bottom-up Fill Conventional Plating
Conformal Plating
(unacceptable) 
Bottom-up Fill
(Good!) 
Void
Conventional Plating
(unacceptable) 

23. ‘Conventional’ Plating
Via-fill modes
VOID
SEAM
‘Conventional’ Plating
Conformal Plating
‘Bottom-up’ Plating

24. Issues in Copper Metallization
‘BOTTOM-UP’ plating of vias
“VOID”
“SEAM”
“Bottom-up”
Special mixture of plating additives can lead to ‘bottom-up’ fill.
However, additives selection is empirical and fundamental information about their role is lacking.

25. What promotes ‘Bottom-up Fill’ ?
Special plating chemistry required for ‘bottom-up’ fill.
PLATING CHEMISTRY:
~ 0.5 M CuSO4 + H2SO ppm Cl- +
Polyether (PEG) ‘INHIBITOR’ ~100 – 400 ppm
Bis(3-sulfopropyl) disulfide (SPS) ‘ACCELERATOR’ ~20 – 50 ppm
2-imidazolidinethione
~2 – 5 ppm
H-(OCH2CH2)n-OH

26. Variable Adsorption leads to Variable Kinetics and to ‘Bottom-up’ fill:
‘Enhancer’, e.g. Organic di-sulfide
Suppressor, e.g. PEG
Slow deposition
Fast deposition

27. Variable Deposition Rates Due to Non-uniform Inhibition
Polarization Curves i
[mA/cm2]
Enhanced Kinetics (via)
100
Suppressed Kinetics
(‘flat’ wafer) 10
300 mV V

28. Key Issues in ‘Bottom-up’ Plating
All metallization chemistries contain :
PEG (inhibitor / suppressor)
SPS (accelerator / anti-suppressor)
Chloride ions
WHY ONLY THESE and NOT OTHERS ???
PEG +
SPS +
Cl- =
GOOD
SPS +
Cl- =
BAD =
BAD
PEG +
SPS
PEG +
Cl- =
BAD

29. Key Issues
Accelerated bottom growth should terminate before top surface is approached
Top surface must remain passivated for only a limited time
Only negligible amount of additives incorporates in the deposit or decomposes: steady-state models inadequate
Via fills in s. – Transient interactions are crucial
Understanding of transient additives transport, adsorption, and interactions.

30. A Few Proposed Mechanisms
IBM’s model
West et al.
Moffat et al.
Adjustable Kinetics along the Via Walls
Curvature Enhanced Accelerator Coverage
Diffusion Controlled Additives Transport
Limitations:
Steady state model
Many arbitrary adjustable parameters.
Unaddressed Issues:
Additives interactions
Unsteady state effects
Unaddressed Issues:
Unsteady state effects
Role of PEG
Arbitrary initial conditions

31. Objectives Characterize the transient additives interactions
Explain and model the bottom-up fill process
Develop a Simulation for the Bottom-Up Fill
Should correlate experimental observations
Without adjustable parameters or extreme assumptions S P
time ?

32. Experimental Setup Plating Conditions: Additives:
RDE
Cu/CuSO4
Reference
Syringe
Additives
Copper plating chemistry
Plating Conditions:
Electrolyte : 0.5 M CuSO4
+ H2SO4 (pH~2)
Galvanostatic : i = 30 mA/cm2
Rotation speed : 200 rpm
Additives:
Chloride ions : ppm
Polyethylene glycol (PEG) : ppm
Bis (3-sulfopropyl)-disodium sulfonate
(SPS) : ppm

33. Cl- essential for PEG assisted polarization
PEG Adsorption – Effect of Cl-
PEG + Cl-
Cl- essential for PEG assisted polarization
No additive
Overpotential (mV)
Only PEG
Only Cl-
Time t (s)
Injection time

34. PEG Adsorption Cl - 200 ppm PEG Overpotential (mV) 100 ppm PEG
Effect of Concentration
200 ppm PEG
100 ppm PEG
50 ppm PEG
Overpotential (mV)
t ~ L2/D ~ 7 s
PEG saturation at ≥ 200 ppm
Cl -
Injection time
Time t (s)

35. FAST ADSORPTION KINETICS
SPS Adsorption on ‘Clean’ Electrode
‘Clean’ Electrode
50 ppm SPS + 70 ppm Cl-
Overpotential (mV)
FAST ADSORPTION KINETICS
Injection time
Time t (s)

36. SLOW depolarization of the electrode* t ~ 100 s
SPS Adsorption on ‘PEG-covered’ Electrode
PEG saturated electrode (+ chloride)
SLOW depolarization of the electrode* t ~ 100 s
20 ppm SPS
Overpotential (mV)
50 ppm SPS
Injection time
Time t (s)
* R. Akolkar and U. Landau, AIChE Proceedings (2003).

37. Interactions dominant during the via-fill period (~20-50 s)
Competitive Adsorption (SPS+PEG)
SLOW depolarization by SPS due to displacement of PEG
Overpotential (mV)
Interactions dominant during the via-fill period (~20-50 s)
FAST polarization by PEG
Injection time
Time t (s)

38. Competitive Adsorption (SPS+PEG)
Disc rotation = 50 rpm
SPS accelerated kinetics
t=50s
t=10s
Slow depolarization by SPS
t=0s
Current Density (mA/cm2)
Time
PEG inhibited kinetics (short time)
Overpotential (mV)

39. Adsorption on ‘clean’ electrode Displaces PEG slowly (t~100 s)
Time Scales for Transport, Adsorption and Interaction
PEG + Cl- V
PEG
SPS
Transport
SLOW (D~10-6 cm2/s)
FAST (D~10-5 cm2/s)
Adsorption on ‘clean’ electrode
VERY FAST
FAST (t~5 s)
Interaction
Cannot displace SPS
Displaces PEG slowly (t~100 s)
t (s)
20 ppm SPS V
t (s)

40. Via-Fill Model: Initial Surface Coverage
Capillary Flow
Consequently -
All PEG (~100 molecules) adsorbs
SPS starts adsorbing on ‘PEG-free’ area
PEG Concentration Gradient Develops
Low V/A
High V/A
SPS
PEG
ADSORPTION on ‘clean’ surface -
PEG adsorbs rapidly
SPS adsorbs slower than PEG

41. SPS ADSORBS RAPIDLY ON ‘PEG-FREE’ VIA BOTTOM
Via-Fill Model: PEG Transport Delay
PEG diffuses slowly + Adsorbs on sidewalls
PEG reaches via bottom after ~10 s
t=8s
t=1s
t=3s
t=6s
PEG surface coverage
SPS ADSORBS RAPIDLY ON ‘PEG-FREE’ VIA BOTTOM
TOP
Normalized Depth z*
BOTTOM
*Via is 0.1 μ dia.,1 μ deep

42. Accelerated Bottom-up Growth
Via-Fill Model: PEG Transport Delay
Accelerated Bottom-up Growth
MORE PEG Coverage
MORE SPS Coverage
*R. Akolkar and U. Landau, J. Electrochem. Soc., 151 (11) C702 (2004)

43. Modeling of Via Fill
Time Dependent Transport Kinetics (‘TTK’) Approach
Via Exterior (I)
Via Interior (II)
BULK I
VIA TOP I
Electrolyte II
1 μ
Wafer Surface
VIA BOTTOM
0.1 μ
Solve for C ( z , t ) and θ ( z , t ) in I and II

44. Modeling of Via Fill – TTK Approach
Additives Transport to the WAFER TOP SURFACE
Concentration Profile given by :
BULK PEG
Diffusion boundary layer NO CONVECTION
60 μ
WAFER TOP SURFACE
Adsorption = k ( 1 – θ )
small features are neglected

45. PEG inhibits flat wafer surface instantaneously (t ~ 3-4 s)
Via Exterior: Flat wafer surface
PEG inhibits flat wafer surface instantaneously (t ~ 3-4 s)
PEG surface coverage
Time t (s)

46. Modeling of Via Fill* Model incorporates (NO Adjustable Parameters):
Additives Transient Processes INSIDE THE VIA
R = 0.1 μ L = μ
Diffusion IN
OUT
Adsorption on the sidewalls
Model incorporates (NO Adjustable Parameters):
Additives Transport (PEG diffusion)
Adsorption on sidewalls (Kinetics)
Additives Interactions (SPS displaces PEG)
*R. Akolkar and U. Landau, Abstract No. 157-E1, 205th ECS Meeting, San Antonio (2004).

47. Modeling of Via Fill – TTK Approach
Transport and Competitive Adsorption of both PEG & SPS
Ni,T
Ni,T=0
Ni,A
Ni,D z
z+z
z=0
z=L
Diffusion IN
OUT
PEG Adsorption :
SPS Adsorption :
PEG Displacement:
SPS ‘Intreractive’ Adsorption :

48. Additives Transient Processes INSIDE THE VIA
Modeling of Via Fill*
Additives Transient Processes INSIDE THE VIA
Adsorption
R = 0.1 μ L = μ
Diffusion IN
OUT
DIFFUSION
ADSORPTION
PEG-SPS INTERACT
PEG Transport
PEG Coverage
SPS Coverage
*R. Akolkar and U. Landau, Abstract No. 157-E1, 205th ECS Meeting, San Antonio (2004).

49. Additives-Assisted Deposition Kinetics Modulated current density
SPS
PEG
COPPER SURFACE
Modulated current density

50. Additives-Assisted Deposition Kinetics Total current density:
COPPER SURFACE
Cu++
SPS
PEG
Total current density:
Deposit thickness:

51. TRANSPORT-ADSORPTION PROCESS (0 < t < 5 s)
ADDITIVES COVERAGE AT SHORT TIMES
PEG
SHORT TIMES
PEG-1s
PEG Surface Coverage
SPS Surface Coverage
TRANSPORT-ADSORPTION PROCESS (0 < t < 5 s)
SPS
SPS-1s
Low PEG High SPS
High PEG Low SPS
VIA TOP
VIA BOTTOM
Distance Into the Via

52. TRANSPORT-ADSORPTION PROCESS (0 < t < 5 s)
ADDITIVES COVERAGE AT SHORT TIMES
SHORT TIMES
PEG Surface Coverage
SPS Surface Coverage
PEG-3s
TRANSPORT-ADSORPTION PROCESS (0 < t < 5 s)
SPS-3s
VIA TOP
VIA BOTTOM
Distance Into the Via

53. TRANSPORT-ADSORPTION PROCESS (0 < t < 5 s)
ADDITIVES COVERAGE AT SHORT TIMES
SHORT TIMES
PEG-5s
PEG Surface Coverage
SPS Surface Coverage
TRANSPORT-ADSORPTION PROCESS (0 < t < 5 s)
SPS-5s
VIA TOP
VIA BOTTOM
Distance Into the Via

54. TRANSPORT-KINETICS REGIME (0 < t < 5 s)
ADDITIVES COVERAGE AT SHORT TIMES
PEG-5s
PEG-1s
PEG Surface Coverage
SPS Surface Coverage
PEG-3s
SPS-5s
TRANSPORT-KINETICS REGIME (0 < t < 5 s)
VIA TOP
VIA BOTTOM
Distance Into the Via

55. PEG displacement by the SPS (t~100 s)
PEG COVERAGE AT LONG TIMES
time
10 s
PEG displacement by the SPS (t~100 s)
40 s
30 s
PEG Surface Coverage
INTERACTION REGIME (5 < t < 100 s)
VIA TOP
VIA BOTTOM
Distance Into the Via, z*

56. SPS displaces the adsorbed PEG (t~100 s)
SPS COVERAGE AT LONG TIMES
INTERACTION REGIME (5 < t < 100 s)
30 s
SPS Surface Coverage
SPS displaces the adsorbed PEG (t~100 s)
20 s
10 s
time
VIA TOP
VIA BOTTOM
Distance Into the Via, z*

57. SPS adsorbs on ‘PEG-covered’ bottom SPS adsorbs on ‘PEG-free’ bottom
SPS - Comparison: Via Top vs. Via Bottom
VIA BOTTOM
SPS adsorbs on ‘PEG-covered’ bottom
SPS Surface Coverage
SPS adsorbs on ‘PEG-free’ bottom
VIA TOP
TRANSPORT-KINETICS
INTERACTIONS
Time (s)

58. SPS displaces the adsorbed PEG PEG diffuses to the via bottom
PEG - Comparison: Via Top vs. Via Bottom
VIA TOP
SPS displaces the adsorbed PEG
VIA BOTTOM
PEG Surface Coverage
PEG diffuses to the via bottom
TRANSPORT-KINETICS
INTERACTIONS
Time (s)

59. Effect of PEG Transport Delay
Flat RDE used to simulate transport to the via
Simulated via top (i=15 mA/cm2, rpm)
Flow affects PEG transport only
Kinetic Resistance (ohm)
Slow PEG transport allows SPS time to adsorb
Simulated via bottom (i=30 mA/cm2, 90rpm)
Injection time
Time t (s)

60. SPS displaces the adsorbed PEG PEG diffuses to the via bottom
COMPARISON: Via Top vs. Via Bottom
VIA TOP
Kinetic Resistance
Time (s)
Corresponds to via top
RDE Experiments
Corresponds to via bottom
LONG TIMES
VIA BOTTOM
SPS displaces the adsorbed PEG
PEG Surface Coverage
PEG diffuses to the via bottom
Time (s)
*R. Akolkar and U. Landau, J. Electrochem. Soc., submitted.

61. Effect of varying surface area on additives coverage
Surface area at via bottom shrinks
PEG bonds weakly and re-equilibrates with the electrolyte
SPS bonds strongly and does not leave surface
SPS (or PEG) do not incorporate appreciably within the deposit
Material balance on SPS:

62. SPS Surface Coverage on the via bottom
SURFACE AREA REDUCTION effects
SPS Coverage from transport modeling + Area Reduction Effects
SPS saturation at the bottom
SPS Coverage predicted by Transport-Kinetics model alone
SPS Surface Coverage on the via bottom
Time (s)
A. C. West, S. Mayer and J. Reid, Electrochem. Solid-State Lett., 4 (7), C50 (2001).
T. P. Moffat et al., Electrochem. Solid-State Lett., 4 (4), C26 (2001).

63. EFFECT OF LOCAL AREA REDUCTION
PEG Coverage predicted by Transport-Kinetics approach alone
PEG Coverage accounting for the Local Area Reduction
PEG Surface Coverage on the via bottom
Complete Removal of the PEG
Time (s)

64. Uniform additives composition everywhere
Modeling the ‘Bottom-up’ Fill*
t = 0 s
Uniform additives composition everywhere
PEG
SPS
* R. Akolkar and U. Landau, J. Electrochem. Soc., accepted for publication.

65. Modeling the ‘Bottom-up’ Fill
t → 0+ s
Fast inhibition on the flat wafer
Fast adsorption of PEG on via sidewalls
PEG
SPS

66. SPS diffuses fast – 20 times faster than PEG
Modeling the ‘Bottom-up’ Fill
t = 1-2 s
SPS diffuses fast – 20 times faster than PEG
Inhibited wafer surface
Fast transport of PEG to upper via sidewalls
PEG
SPS
Fast diffusion and adsorption of SPS on ‘bare’ copper

67. Modeling the ‘Bottom-up’ Fill
t ~ 10 s
Inhibited wafer surface and via sidewalls
PEG
PEG cannot polarize SPS covered surface
SPS

68. SPS slowly depolarizes the wafer surface by displacing PEG
Modeling the ‘Bottom-up’ Fill
t ~ 50 s
SPS slowly depolarizes the wafer surface by displacing PEG
PEG
SPS

69. Summary of Key Aspects of ‘Bottom-up’ Fill
No additives initially inside the via due to the low volume/area ratio.
High volume/area ratio on the wafer top surface leads to instantaneous inhibition by PEG.
Slow transport of diffusion limited PEG to the via bottom ( t ~ 8-10 s ).
The PEG transport delay allows time for fast diffusing SPS to adsorb on the via bottom.
Delayed arrival of PEG cannot displace the stronger adsorbing SPS.

70. Scaling Analysis of Additives Transport
Why is a via with ‘reactive sidewalls’ associated with a large PEG transport delay ?
Time constant t ~ L2/D
For a 1 μ via, the time constant
t ~ 0.02 s
PEG is transported by diffusion from the bulk into the via
No PEG inside the via at t ≈ 0 due to small V/A ratio

71. PEG Transport Delay Non-reactive Sidewalls
Numerical Simulation of PEG Transport
Non-reactive Sidewalls
Reactive Sidewalls
PEG surface coverage at via bottom
PEG transport delay: no PEG at via bottom for ~8 s
Time (s)

72. “μ decreases with time”
One-dimensional Pseudo Steady-State Model
Scaling Analysis
Uniform inhibition on the sidewalls
Infinite Sink at Via Bottom 2R L
Transport-Adsorption Model :
Adsorption Rate
k, μ depends on time –
Short times – Low θ – High k, μ
Long times – High θ – Low k, μ
“μ decreases with time”
Diffusion Rate
Thiele Modulus
where :

73. One-dimensional Transport Kinetics Model
Scaling Approach
Concentration Profiles
μ = 1
Decreasing ‘μ’ due to gradual inhibition of sidewalls
μ = 30
PEG Concentration, C*
No Transport of PEG to the Bottom at high μ’s
Normalized Depth, z*
Via Top
Via Bottom

74. Establishing Relationship Between k and t
In time t :
Amount of PEG Adsorbed on the Sidewalls
Amount of PEG Accumulated in the via
Amount of PEG Entering the Via = +
Assumptions :
Negligible PEG Accumulation
Average Diffusion Flux In :
Linear Time Dependence of k :

75. Normalized Flux of PEG at the via bottom
PEG Transport Delay
Scaling Approach
Normalized Flux of PEG at the via bottom
PEG transport delay: no PEG at via bottom for ~9 s
Uninhibited via sidewalls θside= 0
Inhibited via sidewalls and bottom θ ~ 1
Time t (s)

76. Effect of Via Radius (L=1 μm)
PEG Transport Delay
Effect of Via Radius (L=1 μm)
Inverse dependence of PEG transport delay on via radius
‘Transients’ due to Transport Kinetics significant for high aspect ratios
PEG Transport Delay (s)
INTEL 90nm technology
High Aspect Ratio Vias
Low Aspect Ratio Vias
Via Radius (μm)

77. PEG Transport in Vias with Sloping Sidewalls
How does the via geometry affect the PEG transport characteristic ?
2Ro
2Ro
2Ro Ф Ф
Ф = positive (Outward Sloping) RE-ENTRANT
Ф = (Non-Sloping)
Ф = negative (Inward Sloping)

78. Diffusion IN = Diffusion OUT + Adsorption + Accumulation
One-dimensional Unsteady-State Model
Adsorption
Diffusional Flux IN
OUT
Adsorption
Ф > 0
Ф < 0
Transport Model for a Via with Sloping Reactive Sidewalls :
Diffusion IN = Diffusion OUT + Adsorption + Accumulation
Effect of varying radius stronger on transport
Diffusion =
Adsorption =

79. Surface Coverage at the via bottom (θPEG)
One-dimensional Unsteady-state Model
FASTER Transport
Ф = 0 o
Ф = 10 o
Surface Coverage at the via bottom (θPEG)
Ф = -1.1 o
SLOWER Transport
Time t (s)

80. Transport-kinetics time scale Additives Interaction time scale
Quantitative Modeling of Via-Fill
Time Scales
SHORT
LONG
Transport-kinetics time scale
Additives Interaction time scale
t ≤ 10 s
t > 10 s
PEG
SPS

81. Transport Kinetics Time Scale
SHORT
t ≤ 10 s
Generation of differential plating kinetics between the via top and bottom – initiation of superfill.
Copper deposition preferentially occurs at the via bottom.
PEG
SPS

82. Simulation of Via-Fill
Requires additives distribution
Effect of additives surface coverage on the kinetics
NUMERICAL APPROACH
Solution of the Nernst-Planck Equations or a simplified case (Laplace’s Equation)
Time stepping moving boundary
SEMI-QUANTITATIVE APPROACH
Neglect concentration variations inside the via
Move electrode boundaries on the basis of local kinetics using Faraday’s law

83. Simulation of Deposit Propagation
Variable kinetics + Moving boundaries
Virtual electrode;
Outer edge of diffusion layer
 2  =0
i = f (η) C
 2 C =0
Passivated kinetics (PEG->SPS)
Variable kinetics [Partially passivated, f(t)]
Accelerated kinetics (SPS)

84. Numerical Simulation of Via-Fill – Variable Kinetics*
SiO2
Electrolyte
SiO2
Electrolyte
Fill Time: 48 sec.
Overpotential: mV
Bottom:
i = 60 mA/cm2
Top:
i = 0.24 mA/cm2  3.4 mA/cm2
(Depolarization by SPS)
Sidewalls: Interpolated kinetics between Top and Bottom
‘Cell-Design’ Simulations MOVING BOUNDARIES
* U. Landau, E. Malyshev, R. Akolkar and S. Chivilikhin, AIChE Proceedings (2003).

85. Via Fill Simulation Current density has been lowered: Electrolyte
SiO2
Electrolyte
Seam
Current density has been lowered:
 No Bottom-Up Fill
Plating Time: ~147 sec.
Overpotential: - 80 mV
Bottom:
i = 10 mA/cm2
i0 = 1.12 mA/cm C = 0.83
Top:
i = 0.05 mA/cm2  4.8 mA/cm2
High Depolarization by SPS:
i0 = 3.1 μA/cm2  0.28 mA/cm2
C = 0.9
Sidewalls: Interpolated kinetics between Top and Bottom
1 sec time intervals
‘Cell-Design’ Simulations

86. Flat ‘Bottom-up’ Growth iavg=63 mA/cm2
SIMULATIONS OF THE VIA-FILL
η = 120 mV PEG = 100 ppm SPS = 20 ppm
35 s z*
30 s
VIA-FILL
*V. Dubin, Microelectronic Engineering, 70, 461, 2003.
20 s
Flat ‘Bottom-up’ Growth iavg=63 mA/cm2
10 s r*

87. ‘Conformal Deposition’ Rapid depolarization on the via sidewalls
VIA-FILL SIMULATIONS: Effect of SPS
η = 120 mV PEG = 100 ppm SPS = 0 ppm
Seam after 900 s z*
‘Conformal Deposition’
15 s r* z*
Rapid depolarization on the via sidewalls
‘Center-line’ Voids
η = 120 mV PEG = 100 ppm SPS = 100 ppm r*

88. z* Growth Profile at Low overpotential Seam after 75 s BAD
η = 80 mV PEG = 100 ppm SPS = 20 ppm
Seam after 75 s
GOOD
BAD z*
Bottom cannot escape depolarizing sidewalls
Low ‘bottom-up’ current density i ~ 12 mA/cm2 r*

89. Modeling of Superfill – Effect of Current Density
Cpeg=200 ppm Csps=20 ppm Via AR = 10
V = 130 mV
V = 60 mV
200 s
30 s
Bottom-up growth
‘Seam’ at the mouth due to depolarization by SPS
21 mA/cm2
1 mA/cm2

90. Wafer-scale Modeling Rationale for study
Only wafer-scale parameters, e.g., total current (I) or voltage (V) are measurable
Optimize the process by identifying current/ potential waveforms
Transient nature of wafer-scale processes due to:
Transient additives interactions
Geometry changes during via-fill

91. Empirical observations during wafer metallization:
Wafer-scale Modeling
300 mm wafer
0.2 μ dia., 1 μ deep vias (via loading ~ 6 %)
Empirical observations during wafer metallization:
Current is initiated upon wafer immersion
Initial overall current is low
Current is increased as via-fill is initiated

92. Wafer-scale Modeling Current balance on the entire wafer :
Assuming inhibited sidewall kinetics similar to the wafer top
The wafer geometric current density :

93. Wafer Current Density, mA/cm2
Wafer-scale current transients
η = 0.12 V (constant ‘Driving force’)
Wafer current drops at long times (t>25s)
Wafer Current Density, mA/cm2
Wafer Current, A
Rapid wafer depolarization at short times (t < 10 s)
SPS = 20 ppm PEG = 100 ppm
Time, s

94. Wafer Current Density, mA/cm2
Comparison with Experiments
Model predictions in agreement with experiments
Source: J. Reid et. al.*
Wafer Current Density, mA/cm2
Time, s
* Experimental data: J. Reid et al., Electrochem. Solid-State Lett., 6(2) C26 (2003).

95. Wafer Current Density, mA/cm2
Wafer-scale i vs. t : Effect of potential
η = 0.13 V
VIA-FILL COMPLETION
Wafer Current Density, mA/cm2
η = 0.12 V
SPS = 20 ppm PEG = 100 ppm Via loading = 6.3%
Time, s

96. Wafer Current Density, mA/cm2
Wafer-scale i vs. t : Effect of SPS conc.
SPS = 30 ppm Centerline Voids
Wafer Current Density, mA/cm2
SPS = 20 ppm ‘Defect-free’ Fill
η = 0.12 V PEG = 100 ppm Via loading = 6.3%
Time, s

97. Wafer Current Density, mA/cm2
Wafer-scale i vs. t : Effect of via loading
Via loading = 12.6%
Wafer Current Density, mA/cm2
Via loading = 6.3%
η = 0.12 V PEG = 100 ppm SPS = 20 ppm
Time, s

98. Implication of Constant Current
Wafer Current Density, mA/cm2
Time, s
SPS =` 20 ppm PEG = 100 ppm
η = 0.12 V (constant ‘Driving force’)
Current
Wafer Voltage (mV )
Voltage
Too high – bottom defects
Too low– centerline defects
120
Time, s

99. Major Conclusions
A comprehensive model for the ‘bottom-up’ fill is presented.
WITHOUT invoking any adjustable parameters
Based on experimentally characterized additives effects
The model explains:
Specific role of the PEG and SPS in the multi-component additives system
The effect of operating parameters and via geometry
Wafer-scale current response.

100. Acknowledgements: THANK YOU ALL! Dr. Rohan Akolkar
Case Prime Fellowship to Rohan Akolkar
General Motors Research and Development
The Dept. of Chemical Engineering, CWRU
John D’Urso
David Rear
Mark Bubnick
Applied Materials
Yezdi Dordi
Peter Hey
THANK YOU ALL!

102. Additives Distribution during TK time scale
t = 0 s
PEG Surface Coverage
SPS Surface Coverage
No PEG or SPS on the via sidewalls at t = 0
Normalized depth, z*
Via Top
Via Bottom

103. Additives Distribution during TK time scale
t < 1 s
Inhibited Via Top
PEG-free bottom with some SPS
PEG Surface Coverage
SPS Surface Coverage
Normalized depth, z*
Via Top
Via Bottom

104. Additives Distribution during TK time scale
t ~ 4 s
Inhibited Via Top
Accelerated Via Bottom
PEG Surface Coverage
SPS Surface Coverage
Normalized depth, z*
Via Top
Via Bottom

105. Additives Distribution during TK time scale
t ~ 8 s
High PEG Low SPS
PEG Surface Coverage
SPS Surface Coverage
Low PEG High SPS
Normalized depth, z*
Via Top
Via Bottom