Presentation on theme: "Metallization of Submicron Features Case Western Reserve University"— Presentation transcript:
1 Metallization of Submicron Features Case Western Reserve University inHigh-End Semiconductor Devices by Copper ElectroplatingUziel LandauDepartment of Chemical EngineeringCase Western Reserve UniversityCleveland, OH 44106Presented at ENERGIZER 2/4/05
2 High-Tech: Low-Tech: Technology precedes the science – empiricism CVD, PVD deposition of semiconductorsDrugs developmentCatalysisTechnology precedes the science – empiricismElectroplating (some aspects)Low-Tech:Oil refiningElectrical machinerySteel manufacturingUnderlying science is well-established:
3 Outline Overview of Copper Interconnect Metallization Rationale for this workAnalyzing the additives effects*Experimental InvestigationsModeling of Additives Transport + AdsorptionSimulation of the via-fill processScaling Issues & Wafer-scaleConclusions
5 Recent Microprocessors ~ 70 Million transistors/processor~ 300 Million interconnects/processor~ 200 Processors/200 mm waferMetallized Wafer
6 J. Dahm and K. Monnig, Sematech, AMC 1998 Conf. Proceedings, pp. 3-15. Device Speed vs. SizeTRENCHAl 2.65 μΩ cmCu 1.68 μΩ cmAg 1.59 μΩ cmVIArSiO2GATEDEVICETime Constantt = R CLonger Time delayInterconnect resistance RsmallerGATETo reduce t -Lower resistivity (ρ)Lower dielectric constant (K)INTERCONNECTSmaller line sizeJ. Dahm and K. Monnig, Sematech, AMC 1998 Conf. Proceedings, pp
7 Interconnect Cross-section Moving from Al to Cu InterconnectsAl InterconnectsCu InterconnectsTransistor ‘Gate’
9 Advantages of Copper Metallization Higher conductivityReduced time delayHigher current density at lower powerScalability – finer lines at lower levelsImproved EM performanceFewer steps – Dual Damascene ProcessFewer defectsLess equipment, spaceLower costFaster processingLess costly equipmentEnvironmentally benignIntroduced by IBM (Andricacos, Uzoh, Dukovic, Horkans, Deligianni)Commercially implemented (IBM, Intel, Motorola/AMD, TI,…)
10 Issues in Copper Metallization ‘Attitude’-Extending ‘wet chemistry’ to ‘dry’ semiconductor processingDoubting the ability of plating to meet the challengeMeeting unparalleled requirements of purity and precisionTechnical-Via scale:‘Bottom up’ fillSeed layer in aggressive geometries (<0.2 μm) – continuityWafer scale:Thickness uniformity of the copper over-plateResistive substrate (~1000 A seed)Modeling and scaling (300 mm, current density, flow…)Process Integration
14 Equivalent resistive network RseedIedgeIcenterRseedRelectrolytevvvvvVVapplied= V+- V- == Icenter Relectr.+ Iseed Rseed.= Iedge Relectr.-vvvvvVvvvvvVvvvvvVvvvvvVvvvvvVvvvvvVvvvvvVIedgevvvvvVvvvvvVvvvvvVvvvvvVIcenterRelectrolytevvvvvVvvvvvVvvvvvVRefer to previous work: Tobias, Alkire, LandauSelected results: Phi, Lanzi’sModified Phi (?), modified Lanzi’s definitionvvvvvVvvvvvVvvvvvVvvvvvV+A high resistivity electrolyte will minimize the resistive seed effect
15 Low-acid electrolyte Removing the acid; k : 0.5 0.05 W-1cm-1 Typical acid concentration: MRole of acid: provide conductivityRemoving the acid; k : W-1cm-10.25M CuSO M H2SO4Cu++: l = z = C = 0.25x10-3 M/cm3 kCu++ = W-1cm-1SO4--: l = z = C = 0.25x10-3 M/cm kSO4-- = W-1cm-1H+ : l = z = C = 1.8 x10-3 M/cm kH = W-1cm-1HSO4-: l = z = C = 1.8x10-3 M/cm kHSO4-= 0.09 W-1cm-1kTotal = W-1cm-1
18 Flow Simulations Micro-Scale Transport within the via is due to diffusion‘Cell-Design’ Simulations
19 Enhancing mass transport Flow - reduce d(but inside via only diffusion pertains...)Raise copper conc.: M M (solubility issue -- reducing acid is helpful -common ion effectt (transport number):
20 New electrolyte formulation No or low acidcounteracts the resistive seed effectsupports higher copper solubility‘chemical’ enhancement of transportenvironmental, safety and handling benefitsless corrosiveenhances copper seed stability in the presence of dissolved oxygenHigh copper concentrationenhances transport1~2 M (pH=0) ~ 0.1 M (pH = 1~3.5)M M
21 Rapid Fill of Vias and Trenches 2-3 Min< 50 Sec
24 Issues in Copper Metallization ‘BOTTOM-UP’ plating of vias“VOID”“SEAM”“Bottom-up”Special mixture of plating additives can lead to ‘bottom-up’ fill.However, additives selection is empirical and fundamental information about their role is lacking.
25 What promotes ‘Bottom-up Fill’ ? Special plating chemistry required for ‘bottom-up’ fill.PLATING CHEMISTRY:~ 0.5 M CuSO4 + H2SO ppm Cl- +Polyether (PEG) ‘INHIBITOR’ ~100 – 400 ppmBis(3-sulfopropyl) disulfide (SPS) ‘ACCELERATOR’ ~20 – 50 ppm2-imidazolidinethione~2 – 5 ppmH-(OCH2CH2)n-OH
26 Variable Adsorption leads to Variable Kinetics and to ‘Bottom-up’ fill: ‘Enhancer’, e.g. Organic di-sulfideSuppressor, e.g. PEGSlow depositionFast deposition
27 Variable Deposition Rates Due to Non-uniform Inhibition Polarization Curvesi[mA/cm2]Enhanced Kinetics (via)100Suppressed Kinetics(‘flat’ wafer)10300 mVV
28 Key Issues in ‘Bottom-up’ Plating All metallization chemistries contain :PEG (inhibitor / suppressor)SPS (accelerator / anti-suppressor)Chloride ionsWHY ONLY THESE and NOT OTHERS ???PEG+SPS+Cl-=GOODSPS+Cl-=BAD=BADPEG+SPSPEG+Cl-=BAD
29 Key IssuesAccelerated bottom growth should terminate before top surface is approachedTop surface must remain passivated for only a limited timeOnly negligible amount of additives incorporates in the deposit or decomposes: steady-state models inadequateVia fills in s. – Transient interactions are crucialUnderstanding of transient additives transport, adsorption, and interactions.
30 A Few Proposed Mechanisms IBM’s modelWest et al.Moffat et al.Adjustable Kinetics along the Via WallsCurvature Enhanced Accelerator CoverageDiffusion Controlled Additives TransportLimitations:Steady state modelMany arbitrary adjustable parameters.Unaddressed Issues:Additives interactionsUnsteady state effectsUnaddressed Issues:Unsteady state effectsRole of PEGArbitrary initial conditions
31 Objectives Characterize the transient additives interactions Explain and model the bottom-up fill processDevelop a Simulation for the Bottom-Up FillShould correlate experimental observationsWithout adjustable parameters or extreme assumptionsSPtime ?
33 Cl- essential for PEG assisted polarization PEG Adsorption – Effect of Cl-PEG + Cl-Cl- essential for PEG assisted polarizationNo additiveOverpotential (mV)Only PEGOnly Cl-Time t (s)Injection time
34 PEG Adsorption Cl - 200 ppm PEG Overpotential (mV) 100 ppm PEG Effect of Concentration200 ppm PEG100 ppm PEG50 ppm PEGOverpotential (mV)t ~ L2/D ~ 7 sPEG saturation at ≥ 200 ppmCl -Injection timeTime t (s)
35 FAST ADSORPTION KINETICS SPS Adsorption on ‘Clean’ Electrode‘Clean’ Electrode50 ppm SPS + 70 ppm Cl-Overpotential (mV)FAST ADSORPTION KINETICSInjection timeTime t (s)
36 SLOW depolarization of the electrode* t ~ 100 s SPS Adsorption on ‘PEG-covered’ ElectrodePEG saturated electrode (+ chloride)SLOW depolarization of the electrode* t ~ 100 s20 ppm SPSOverpotential (mV)50 ppm SPSInjection timeTime t (s)* R. Akolkar and U. Landau, AIChE Proceedings (2003).
37 Interactions dominant during the via-fill period (~20-50 s) Competitive Adsorption (SPS+PEG)SLOW depolarization by SPS due to displacement of PEGOverpotential (mV)Interactions dominant during the via-fill period (~20-50 s)FAST polarization by PEGInjection timeTime t (s)
41 SPS ADSORBS RAPIDLY ON ‘PEG-FREE’ VIA BOTTOM Via-Fill Model: PEG Transport DelayPEG diffuses slowly + Adsorbs on sidewallsPEG reaches via bottom after ~10 st=8st=1st=3st=6sPEG surface coverageSPS ADSORBS RAPIDLY ON ‘PEG-FREE’ VIA BOTTOMTOPNormalized Depth z*BOTTOM*Via is 0.1 μ dia.,1 μ deep
42 Accelerated Bottom-up Growth Via-Fill Model: PEG Transport DelayAccelerated Bottom-up GrowthMORE PEG CoverageMORE SPS Coverage*R. Akolkar and U. Landau, J. Electrochem. Soc., 151 (11) C702 (2004)
43 Modeling of Via FillTime Dependent Transport Kinetics (‘TTK’) ApproachVia Exterior (I)Via Interior (II)BULKIVIA TOPIElectrolyteII1 μWafer SurfaceVIA BOTTOM0.1 μSolve for C ( z , t ) and θ ( z , t ) in I and II
44 Modeling of Via Fill – TTK Approach Additives Transport to the WAFER TOP SURFACEConcentration Profile given by :BULK PEGDiffusion boundary layer NO CONVECTION60 μWAFER TOP SURFACEAdsorption = k ( 1 – θ )small features are neglected
45 PEG inhibits flat wafer surface instantaneously (t ~ 3-4 s) Via Exterior: Flat wafer surfacePEG inhibits flat wafer surface instantaneously (t ~ 3-4 s)PEG surface coverageTime t (s)
46 Modeling of Via Fill* Model incorporates (NO Adjustable Parameters): Additives Transient Processes INSIDE THE VIAR = 0.1 μ L = μDiffusion INOUTAdsorption on the sidewallsModel incorporates (NO Adjustable Parameters):Additives Transport (PEG diffusion)Adsorption on sidewalls (Kinetics)Additives Interactions (SPS displaces PEG)*R. Akolkar and U. Landau, Abstract No. 157-E1, 205th ECS Meeting, San Antonio (2004).
47 Modeling of Via Fill – TTK Approach Transport and Competitive Adsorption of both PEG & SPSNi,TNi,T=0Ni,ANi,Dzz+zz=0z=LDiffusion INOUTPEG Adsorption :SPS Adsorption :PEG Displacement:SPS ‘Intreractive’ Adsorption :
48 Additives Transient Processes INSIDE THE VIA Modeling of Via Fill*Additives Transient Processes INSIDE THE VIAAdsorptionR = 0.1 μ L = μDiffusion INOUTDIFFUSIONADSORPTIONPEG-SPS INTERACTPEG TransportPEG CoverageSPS Coverage*R. Akolkar and U. Landau, Abstract No. 157-E1, 205th ECS Meeting, San Antonio (2004).
49 Additives-Assisted Deposition Kinetics Modulated current density SPSPEGCOPPER SURFACEModulated current density
50 Additives-Assisted Deposition Kinetics Total current density: COPPER SURFACECu++SPSPEGTotal current density:Deposit thickness:
51 TRANSPORT-ADSORPTION PROCESS (0 < t < 5 s) ADDITIVES COVERAGE AT SHORT TIMESPEGSHORT TIMESPEG-1sPEG Surface CoverageSPS Surface CoverageTRANSPORT-ADSORPTION PROCESS (0 < t < 5 s)SPSSPS-1sLow PEG High SPSHigh PEG Low SPSVIA TOPVIA BOTTOMDistance Into the Via
52 TRANSPORT-ADSORPTION PROCESS (0 < t < 5 s) ADDITIVES COVERAGE AT SHORT TIMESSHORT TIMESPEG Surface CoverageSPS Surface CoveragePEG-3sTRANSPORT-ADSORPTION PROCESS (0 < t < 5 s)SPS-3sVIA TOPVIA BOTTOMDistance Into the Via
53 TRANSPORT-ADSORPTION PROCESS (0 < t < 5 s) ADDITIVES COVERAGE AT SHORT TIMESSHORT TIMESPEG-5sPEG Surface CoverageSPS Surface CoverageTRANSPORT-ADSORPTION PROCESS (0 < t < 5 s)SPS-5sVIA TOPVIA BOTTOMDistance Into the Via
54 TRANSPORT-KINETICS REGIME (0 < t < 5 s) ADDITIVES COVERAGE AT SHORT TIMESPEG-5sPEG-1sPEG Surface CoverageSPS Surface CoveragePEG-3sSPS-5sTRANSPORT-KINETICS REGIME (0 < t < 5 s)VIA TOPVIA BOTTOMDistance Into the Via
55 PEG displacement by the SPS (t~100 s) PEG COVERAGE AT LONG TIMEStime10 sPEG displacement by the SPS (t~100 s)40 s30 sPEG Surface CoverageINTERACTION REGIME (5 < t < 100 s)VIA TOPVIA BOTTOMDistance Into the Via, z*
56 SPS displaces the adsorbed PEG (t~100 s) SPS COVERAGE AT LONG TIMESINTERACTION REGIME (5 < t < 100 s)30 sSPS Surface CoverageSPS displaces the adsorbed PEG (t~100 s)20 s10 stimeVIA TOPVIA BOTTOMDistance Into the Via, z*
57 SPS adsorbs on ‘PEG-covered’ bottom SPS adsorbs on ‘PEG-free’ bottom SPS - Comparison: Via Top vs. Via BottomVIA BOTTOMSPS adsorbs on ‘PEG-covered’ bottomSPS Surface CoverageSPS adsorbs on ‘PEG-free’ bottomVIA TOPTRANSPORT-KINETICSINTERACTIONSTime (s)
58 SPS displaces the adsorbed PEG PEG diffuses to the via bottom PEG - Comparison: Via Top vs. Via BottomVIA TOPSPS displaces the adsorbed PEGVIA BOTTOMPEG Surface CoveragePEG diffuses to the via bottomTRANSPORT-KINETICSINTERACTIONSTime (s)
59 Effect of PEG Transport Delay Flat RDE used to simulate transport to the viaSimulated via top (i=15 mA/cm2, rpm)Flow affects PEG transport onlyKinetic Resistance (ohm)Slow PEG transport allows SPS time to adsorbSimulated via bottom (i=30 mA/cm2, 90rpm)Injection timeTime t (s)
60 SPS displaces the adsorbed PEG PEG diffuses to the via bottom COMPARISON: Via Top vs. Via BottomVIA TOPKinetic ResistanceTime (s)Corresponds to via topRDE ExperimentsCorresponds to via bottomLONG TIMESVIA BOTTOMSPS displaces the adsorbed PEGPEG Surface CoveragePEG diffuses to the via bottomTime (s)*R. Akolkar and U. Landau, J. Electrochem. Soc., submitted.
61 Effect of varying surface area on additives coverage Surface area at via bottom shrinksPEG bonds weakly and re-equilibrates with the electrolyteSPS bonds strongly and does not leave surfaceSPS (or PEG) do not incorporate appreciably within the depositMaterial balance on SPS:
62 SPS Surface Coverage on the via bottom SURFACE AREA REDUCTION effectsSPS Coverage from transport modeling + Area Reduction EffectsSPS saturation at the bottomSPS Coverage predicted by Transport-Kinetics model aloneSPS Surface Coverage on the via bottomTime (s)A. C. West, S. Mayer and J. Reid, Electrochem. Solid-State Lett., 4 (7), C50 (2001).T. P. Moffat et al., Electrochem. Solid-State Lett., 4 (4), C26 (2001).
63 EFFECT OF LOCAL AREA REDUCTION PEG Coverage predicted by Transport-Kinetics approach alonePEG Coverage accounting for the Local Area ReductionPEG Surface Coverage on the via bottomComplete Removal of the PEGTime (s)
64 Uniform additives composition everywhere Modeling the ‘Bottom-up’ Fill*t = 0 sUniform additives composition everywherePEGSPS* R. Akolkar and U. Landau, J. Electrochem. Soc., accepted for publication.
65 Modeling the ‘Bottom-up’ Fill t → 0+ sFast inhibition on the flat waferFast adsorption of PEG on via sidewallsPEGSPS
66 SPS diffuses fast – 20 times faster than PEG Modeling the ‘Bottom-up’ Fillt = 1-2 sSPS diffuses fast – 20 times faster than PEGInhibited wafer surfaceFast transport of PEG to upper via sidewallsPEGSPSFast diffusion and adsorption of SPS on ‘bare’ copper
67 Modeling the ‘Bottom-up’ Fill t ~ 10 sInhibited wafer surface and via sidewallsPEGPEG cannot polarize SPS covered surfaceSPS
68 SPS slowly depolarizes the wafer surface by displacing PEG Modeling the ‘Bottom-up’ Fillt ~ 50 sSPS slowly depolarizes the wafer surface by displacing PEGPEGSPS
69 Summary of Key Aspects of ‘Bottom-up’ Fill No additives initially inside the via due to the low volume/area ratio.High volume/area ratio on the wafer top surface leads to instantaneous inhibition by PEG.Slow transport of diffusion limited PEG to the via bottom ( t ~ 8-10 s ).The PEG transport delay allows time for fast diffusing SPS to adsorb on the via bottom.Delayed arrival of PEG cannot displace the stronger adsorbing SPS.
70 Scaling Analysis of Additives Transport Why is a via with ‘reactive sidewalls’ associated with a large PEG transport delay ?Time constant t ~ L2/DFor a 1 μ via, the time constantt ~ 0.02 sPEG is transported by diffusion from the bulk into the viaNo PEG inside the via at t ≈ 0 due to small V/A ratio
71 PEG Transport Delay Non-reactive Sidewalls Numerical Simulation of PEG TransportNon-reactive SidewallsReactive SidewallsPEG surface coverage at via bottomPEG transport delay: no PEG at via bottom for ~8 sTime (s)
72 “μ decreases with time” One-dimensional Pseudo Steady-State ModelScaling AnalysisUniform inhibition on the sidewallsInfinite Sink at Via Bottom2RLTransport-Adsorption Model :Adsorption Ratek, μ depends on time –Short times – Low θ – High k, μLong times – High θ – Low k, μ“μ decreases with time”Diffusion RateThiele Moduluswhere :
73 One-dimensional Transport Kinetics Model Scaling ApproachConcentration Profilesμ = 1Decreasing ‘μ’ due to gradual inhibition of sidewallsμ = 30PEG Concentration, C*No Transport of PEG to the Bottom at high μ’sNormalized Depth, z*Via TopVia Bottom
74 Establishing Relationship Between k and t In time t :Amount of PEG Adsorbed on the SidewallsAmount of PEG Accumulated in the viaAmount of PEG Entering the Via=+Assumptions :Negligible PEG AccumulationAverage Diffusion Flux In :Linear Time Dependence of k :
75 Normalized Flux of PEG at the via bottom PEG Transport DelayScaling ApproachNormalized Flux of PEG at the via bottomPEG transport delay: no PEG at via bottom for ~9 sUninhibited via sidewalls θside= 0Inhibited via sidewalls and bottom θ ~ 1Time t (s)
76 Effect of Via Radius (L=1 μm) PEG Transport DelayEffect of Via Radius (L=1 μm)Inverse dependence of PEG transport delay on via radius‘Transients’ due to Transport Kinetics significant for high aspect ratiosPEG Transport Delay (s)INTEL 90nm technologyHigh Aspect Ratio ViasLow Aspect Ratio ViasVia Radius (μm)
77 PEG Transport in Vias with Sloping Sidewalls How does the via geometry affect the PEG transport characteristic ?2Ro2Ro2RoФФФ = positive (Outward Sloping) RE-ENTRANTФ = (Non-Sloping)Ф = negative (Inward Sloping)
78 Diffusion IN = Diffusion OUT + Adsorption + Accumulation One-dimensional Unsteady-State ModelAdsorptionDiffusional Flux INOUTAdsorptionФ > 0Ф < 0Transport Model for a Via with Sloping Reactive Sidewalls :Diffusion IN = Diffusion OUT + Adsorption + AccumulationEffect of varying radius stronger on transportDiffusion =Adsorption =
79 Surface Coverage at the via bottom (θPEG) One-dimensional Unsteady-state ModelFASTER TransportФ = 0 oФ = 10 oSurface Coverage at the via bottom (θPEG)Ф = -1.1 oSLOWER TransportTime t (s)
80 Transport-kinetics time scale Additives Interaction time scale Quantitative Modeling of Via-FillTime ScalesSHORTLONGTransport-kinetics time scaleAdditives Interaction time scalet ≤ 10 st > 10 sPEGSPS
81 Transport Kinetics Time Scale SHORTt ≤ 10 sGeneration of differential plating kinetics between the via top and bottom – initiation of superfill.Copper deposition preferentially occurs at the via bottom.PEGSPS
82 Simulation of Via-Fill Requires additives distributionEffect of additives surface coverage on the kineticsNUMERICAL APPROACHSolution of the Nernst-Planck Equations or a simplified case (Laplace’s Equation)Time stepping moving boundarySEMI-QUANTITATIVE APPROACHNeglect concentration variations inside the viaMove electrode boundaries on the basis of local kinetics using Faraday’s law
83 Simulation of Deposit Propagation Variable kinetics + Moving boundariesVirtual electrode;Outer edge of diffusion layer 2 =0i = f (η)C 2 C =0Passivated kinetics (PEG->SPS)Variable kinetics [Partially passivated, f(t)]Accelerated kinetics (SPS)
84 Numerical Simulation of Via-Fill – Variable Kinetics* SiO2ElectrolyteSiO2ElectrolyteFill Time: 48 sec.Overpotential: mVBottom:i = 60 mA/cm2Top:i = 0.24 mA/cm2 3.4 mA/cm2(Depolarization by SPS)Sidewalls: Interpolated kinetics between Top and Bottom‘Cell-Design’ Simulations MOVING BOUNDARIES* U. Landau, E. Malyshev, R. Akolkar and S. Chivilikhin, AIChE Proceedings (2003).
85 Via Fill Simulation Current density has been lowered: Electrolyte SiO2ElectrolyteSeamCurrent density has been lowered: No Bottom-Up FillPlating Time: ~147 sec.Overpotential: - 80 mVBottom:i = 10 mA/cm2i0 = 1.12 mA/cm C = 0.83Top:i = 0.05 mA/cm2 4.8 mA/cm2High Depolarization by SPS:i0 = 3.1 μA/cm2 0.28 mA/cm2C = 0.9Sidewalls: Interpolated kinetics between Top and Bottom1 sec time intervals‘Cell-Design’ Simulations
87 ‘Conformal Deposition’ Rapid depolarization on the via sidewalls VIA-FILL SIMULATIONS: Effect of SPSη = 120 mV PEG = 100 ppm SPS = 0 ppmSeam after 900 sz*‘Conformal Deposition’15 sr*z*Rapid depolarization on the via sidewalls‘Center-line’ Voidsη = 120 mV PEG = 100 ppm SPS = 100 ppmr*
88 z* Growth Profile at Low overpotential Seam after 75 s BAD η = 80 mV PEG = 100 ppm SPS = 20 ppmSeam after 75 sGOODBADz*Bottom cannot escape depolarizing sidewallsLow ‘bottom-up’ current density i ~ 12 mA/cm2r*
89 Modeling of Superfill – Effect of Current Density Cpeg=200 ppm Csps=20 ppm Via AR = 10V = 130 mVV = 60 mV200 s30 sBottom-up growth‘Seam’ at the mouth due to depolarization by SPS21 mA/cm21 mA/cm2
90 Wafer-scale Modeling Rationale for study Only wafer-scale parameters, e.g., total current (I) or voltage (V) are measurableOptimize the process by identifying current/ potential waveformsTransient nature of wafer-scale processes due to:Transient additives interactionsGeometry changes during via-fill
91 Empirical observations during wafer metallization: Wafer-scale Modeling300 mm wafer0.2 μ dia., 1 μ deep vias (via loading ~ 6 %)Empirical observations during wafer metallization:Current is initiated upon wafer immersionInitial overall current is lowCurrent is increased as via-fill is initiated
92 Wafer-scale Modeling Current balance on the entire wafer : Assuming inhibited sidewall kinetics similar to the wafer topThe wafer geometric current density :
93 Wafer Current Density, mA/cm2 Wafer-scale current transientsη = 0.12 V (constant ‘Driving force’)Wafer current drops at long times (t>25s)Wafer Current Density, mA/cm2Wafer Current, ARapid wafer depolarization at short times (t < 10 s)SPS = 20 ppm PEG = 100 ppmTime, s
94 Wafer Current Density, mA/cm2 Comparison with ExperimentsModel predictions in agreement with experimentsSource: J. Reid et. al.*Wafer Current Density, mA/cm2Time, s* Experimental data: J. Reid et al., Electrochem. Solid-State Lett., 6(2) C26 (2003).
95 Wafer Current Density, mA/cm2 Wafer-scale i vs. t : Effect of potentialη = 0.13 VVIA-FILL COMPLETIONWafer Current Density, mA/cm2η = 0.12 VSPS = 20 ppm PEG = 100 ppm Via loading = 6.3%Time, s
96 Wafer Current Density, mA/cm2 Wafer-scale i vs. t : Effect of SPS conc.SPS = 30 ppm Centerline VoidsWafer Current Density, mA/cm2SPS = 20 ppm ‘Defect-free’ Fillη = 0.12 V PEG = 100 ppm Via loading = 6.3%Time, s
97 Wafer Current Density, mA/cm2 Wafer-scale i vs. t : Effect of via loadingVia loading = 12.6%Wafer Current Density, mA/cm2Via loading = 6.3%η = 0.12 V PEG = 100 ppm SPS = 20 ppmTime, s
98 Implication of Constant Current Wafer Current Density, mA/cm2Time, sSPS =` 20 ppm PEG = 100 ppmη = 0.12 V (constant ‘Driving force’)CurrentWafer Voltage (mV )VoltageToo high – bottom defectsToo low– centerline defects120Time, s
99 Major ConclusionsA comprehensive model for the ‘bottom-up’ fill is presented.WITHOUT invoking any adjustable parametersBased on experimentally characterized additives effectsThe model explains:Specific role of the PEG and SPS in the multi-component additives systemThe effect of operating parameters and via geometryWafer-scale current response.
100 Acknowledgements: THANK YOU ALL! Dr. Rohan Akolkar Case Prime Fellowship to Rohan AkolkarGeneral Motors Research and DevelopmentThe Dept. of Chemical Engineering, CWRUJohn D’UrsoDavid RearMark BubnickApplied MaterialsYezdi DordiPeter HeyTHANK YOU ALL!