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HINS BPM Overview N. Eddy For Instrumentation Dept.

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Presentation on theme: "HINS BPM Overview N. Eddy For Instrumentation Dept."— Presentation transcript:

1 HINS BPM Overview N. Eddy For Instrumentation Dept

2 BPM Hardware Overview 2 BPF LPF Trig Down Mix Cal (xxx) Timing (VME) LO (665) CLK (81.25) TRG Digital Receiver (VME) VME µP Motorola 5500 Q I beam position 4 button BPM pickup IF (15) beam VME BUS LAN PLL 4 ATT 4 CAN CTRL 325

3 Analog Signal Processing 4-ch. Analog downmixer – IN: 650 (2 nd harmonic), LO: 665.1, IF: 15.1 MHz – CAN-bus controlled gain, attenuator & cal system – Gain switchable, low-noise, high IP3 input gain stage – Image rejection (SSB) mixer – ~30 dB gain, ultralinear IF stage 3 15.145 MHz BPF ATT LNA BPF LNA LPF SSB Mixer LO 0°0° 90° LNA LPF Directional Coupler IN 714MHz CF: 650MHz BW: 10MHz G: 14/-2 dB NF: 1dB 0 - 28 dB 4 dB steps 1.6 dB loss 665.1 MHz CF: 15.1 MHz BW: 4MHz G: 18 dBBW: 40 MHz OUT BW: 800 MHz G: 15 dB NF: 1dB Cal Tone Signal

4 8-Ch,14-bit, 125 MS/s VME Digitizer 4 BLOCK DIAGRAM FPGA Altera Cyclone III VME Drivers 4x32M DDR2 SDRAM JTAG EPCS4 Interface VME bus Oscillator CLK IN CLK OUT GATE TRIGGER TCLK SYNC IN SYNC OUT Generic Digitizer External Control Clock Driver (PLL & DIV) ADCADC ADCADC AC passive 8 Analog Inputs 4 Channels per Chip 125 MSPS, 500 MHz BW 4-ch serial ADC chips 8-ch, AC passive (or DC active) PLL/VCO CLK distribution SNR > 72 dB (@50 MHz)

5 FPGA Block Diagram 5 ADC Input 14 Bits 69 MHz NB Filter 1.4kHz output 16 Bits/ch 32 ch / NB Gate WB Gate(s) DDR RAM NB Data TBT Data Raw Data Σ 50Hz VME NB Data VME Raw Data TBT Filter DDC & average VME TBT Data 8 ch / Trigger DAQ SM Ch delays (clocks) Gates in Turns WB Gate(s) NB Gate 32 Registers VME NB Sums VME IRQ resetlatch reset latch 16 ch /

6 Narrowband Signal Processing Design footprint for 8 ADC channels 2 NCOs for beam and cal frequencies -> 16 DDCs 32 CIC Filters operating at 69 MHz 5 stage CIC uses 13 k LEs and <1% of RAM 1 Serial FIR Filter will process all 32 CIC Filter outputs 76 tap FIR (400 Hz BW, 500 Hz Stop, -120 db stopband) Decimate by 3 to 1.4 KSPS output 6 ADC Input 14 Bits 69 MHz X NCO (sin, cos) 24 Bits Phase (~1 Hz) I Q 16 Bits CIC 5 Stages R=16485 DDC 24 Bits 4.2 KSPS FIR (76 taps) LPF 500Hz Decimate 3 Bit Shift Select Significant Bits 20 Bits 4.2 KSPS 16 Bits 1.4 KSPS I Q - Denotes Peak Detectors to optimize scaling 28 pts ave to notch 50 Hz

7 Software Components 7 VME ECAN-2 PMC (1x) VME Timing K-TGF (1x) VME Digitizer (12x) CLK (64.9) TRG (Gate) A B C D 714 2.16 INJ (BIS) 729 CAN Class ADC Interrupt I/Q Data DDC Configure Class KTGF Bucket Delay Turn Data Sample Count Class CALBox Control Status Class ATFBPM Class ATFBPMC AL Control Status Sample Control Interrupt Control Pos/ Int Data EPICS IOC Control Status Flash WB / NB Single/Multi-turn Diag. Mode Bucket Delay Turn Delay Diagnostic Flash Orbit Multi-turn VME HardwareMotorola 5500 µP Software (VxWorks) Ethernet

8 Raw Signals from 4/20/11 BPM 1 BPM 3 BPM 2 BPM 1 BPM 3 BPM 2

9 FFT of RAW Signals for 1 st BPM

10 DDC with Boxcar Filter ~4MHz BW Magn Diff/Sum filtered Sum filtered Magn Diff/Sum filtered Sum filtered

11 Questions What information is desired from the BPM? BW and update rate over the pulse? – Could have WB arrays & pulse averages Phase measurement (???) – Should produce relative phase along bpms able to detect changes in TOF – Could produce absolute phase if we make a reference bpm from RF… needs some further thought

12 Summary Hardware for standard bpms completely installed and working Firmware/Software for ATF project – Currently only provides 1024 ADC samples – Need to decide exactly what the Firmware should do…

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