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1 A Monolithic Low-Bandwidth Jitter- Cleaning PLL with Hitless Switching for SONET/SDH Clock Generation D. Wei, Y. Huang, B. Garlepp and J. Hein Silicon.

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Presentation on theme: "1 A Monolithic Low-Bandwidth Jitter- Cleaning PLL with Hitless Switching for SONET/SDH Clock Generation D. Wei, Y. Huang, B. Garlepp and J. Hein Silicon."— Presentation transcript:

1 1 A Monolithic Low-Bandwidth Jitter- Cleaning PLL with Hitless Switching for SONET/SDH Clock Generation D. Wei, Y. Huang, B. Garlepp and J. Hein Silicon Laboratories Inc., Austin, Texas Presented in ISSCC, Feb, 2006

2 2 New Breed of Analog Designers: digAnalog Requirement for analog interface is higher and higher (i.e. multimedia application), yet technology advancement shies away from the analog performance –Example: 1/f noise, gate leakage, device non-ideality Digital signal processing is so powerful today! –Deep sub-micron CMOS –More computation power for limited-size area Integration is the trend –Consumer electronics require compactness –Delicate process means higher ASP and lower revenues Q: can we enhance the analog performance by the power of digital?

3 3 Insights of Analog-to-digital Interface Go against the technology trend

4 4 Insights of Analog-to-digital Interface (cont) Demand faster technology but with less accuracy!

5 5 digAnalog Design Rules Good understanding of the system requirements –To dig or not to dig, that is the question Pick the right candidate (voltage, current, flux, phase, …) to process –What defines your signal? Faster technology available (and cheap!) –signal bandwidth vs. sampling clock

6 6 Example: Switch References in PLL

7 7 What should I digitize?

8 8 SONET/SDH Clock Management 100% Redundancy is required at the line-card timing reference

9 9 Type-II PLL Phase Transient During Reference-switching max : maximum phase deviation t : maximum phase step slope

10 10 Maximum Time Interval Error (MTIE) Phase Offset (25.7ns max) Frequency Offset (9.2ppm max) Typical LBW choice: 250Hz (clk rearrangement) ~ 1KHz( frequency translation) slope < 81ns/1.326ms

11 11 Hitless Phase-Switching Architecture t=t 1, selA=1 / selB=0 A - offsetA,0 = out,1, offsetB,1 = B t=t 2, selA=0 / selB=1 B - offsetB,1 = out,2, offsetA,2 = A out,1,2 = ( A - B )-( offsetA,0 - offsetB,1 ) = 0 if A and B ~ constant

12 12 Digital Implementation of Hitless Switching (1) PLL LBW < 12KHz PFD ADC f s = 311MHz

13 13 PFD ADC and Auto-zero Loop Loop Bandwidth 22bits PFD full scale = 6.42ns Offset DAC LSB ~ 100ps shift the offset DAC value AZ bandwidth ~ 100KHz D avoids the DAC overflow

14 14 What if Frequency Error Is Present? out,1,2 = ( A - B ) - ( offsetA - offsetB ) – k (0.5 2FS PD ) 8FS PD offset,max = FS PD modulus (k= 0~7) 2FS PD : Phase Detector Full-scale (6.42ns)

15 15 Digital Implementation of Hitless Switching (2) Each swallow: T = 8T vco

16 16 Phase Transient Measurement Setup Linear phase detector demodulates the DUT output phase LOS (loss-of-signal) on clkB triggers the oscilloscope adjustable

17 17 Measured Phase Transient During Reference-switching Mode: Auto-switching (LOS triggers the switching) LOSB trigger the switching Wandering due to LOS Loop relocks the phase residual = 35ps 116ps Initial = 180 (~25ns) PD out LOSB

18 18 Removing the External Loop Filter DSP implementation replaces the bulky external loop filters (LF) Less Bill-of-Materials (BOM) Avoid excess noise-coupling at post-LF nodes

19 19 DSP-based Loop Filter Implementation Gain ratio controls LBW and peaking No external loop filter components needed

20 20 PLL Bandwidth and Peaking Control Feedforward (F) Integration (I) PFD ADC feedforward bits added Input bits accumulated varactor codes Reduced by (rounding) K F ~ LBW / (K PD x K v ) K I ~ (LBW) 2 x ( -1) / (K PD x K v ) For Type-II PLL with low-peaking ( <0.1dB),

21 21 Connecting the Loop Filter to Varactors 2 nd -order generates varactor cntl. voltage DAC expander reduces the analog hardware cost by 16x

22 22 VCO Varactor Implementation

23 23 Varactor DAC and Multiplexer At any instant, only 8 varactors receive DAC tuning voltages

24 24 DAC Movement Across Sub-Varactor Accumulator bits slowly move the DAC banks Feedforward bits vary the tuning voltage V g

25 25 Chip Micrograph PFD/ADC B PFD/ADC F PFD/ADC A output drivers DAC expander multiplexer varactor master regulator VCO divider digital routes / regulators reference generator. 5.1mm 3.5mm

26 26 Discrete Solution vs. Integrated Solution No external loop filters are required. dramatically simplifies the line card design! 50mm discrete solution hybrid solution 23mm 11mm presented solution

27 27 PLL Characteristics Measurement Measured integrated jitter: OC48 band 0.69ps OC192 band 0.26ps 100M101001K10K100K1M10M Frequency (Hz) L(f) (dBc/Hz) Phase LBW=800Hz MHz Output Jitter Generation Measured peaking: < 0.1dB Frequency (Hz) 1001K10K Loop Transfer (dB) 800Hz 1600Hz 3200Hz 6400Hz Jitter Transfer Mhz Input MHz Output

28 28 Performance Summary Technology CMOS Die Size 3.5mm by 5.1mm Package 11 X 11 CBGA Vdd=3.3V 350mW Supported PLL Bandwidth (LBW) 800Hz, 1600Hz, 3200Hz, 6400Hz Loop Transfer Peaking <0.1dB During Reference BW=800Hz Maximum Output Phase Step 200ps Maximum Output Phase Slope (MTIE: <61.08 ns/ms for 3/4E) 4.5 ns/ms Jitter BW=800Hz OC-48 band (12KHz ~ 20MHz) 0.8ps (WC) OC-192 band (50KHz ~ 80MHz) 0.4ps (WC)

29 29 Conclusion Digital hitless clock-switching is demonstrated, enabling the on-chip implementation for SONET/SDH clock management. Loop components are digitally implemented, which minimizes the external noise coupling and also has the good control over loop characteristics. Concise digital implementation of digital varactors simplifies the hardware implementation, and enhances the VCO performance, enabling the jitter-cleaning to the PLL input clocks.

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