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D. Wei, Y. Huang, B. Garlepp and J. Hein

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Presentation on theme: "D. Wei, Y. Huang, B. Garlepp and J. Hein"— Presentation transcript:

1 A Monolithic Low-Bandwidth Jitter-Cleaning PLL with Hitless Switching for SONET/SDH Clock Generation
D. Wei, Y. Huang, B. Garlepp and J. Hein Silicon Laboratories Inc., Austin, Texas Presented in ISSCC, Feb, 2006

2 New Breed of Analog Designers: digAnalog
Requirement for analog interface is higher and higher (i.e. multimedia application), yet technology advancement shies away from the analog performance Example: 1/f noise, gate leakage, device non-ideality Digital signal processing is so powerful today! Deep sub-micron CMOS More computation power for limited-size area Integration is the trend Consumer electronics require compactness Delicate process means higher ASP and lower revenues Q: can we enhance the “analog” performance by the power of “digital”?

3 Insights of Analog-to-digital Interface
 Go against the technology trend

4 Insights of Analog-to-digital Interface (con’t)
 Demand faster technology but with less accuracy!

5 digAnalog Design Rules
Good understanding of the system requirements “To dig or not to dig, that is the question” Pick the right “candidate” (voltage, current, flux, phase, …) to process What defines your “signal”? Faster technology available (and cheap!) signal bandwidth vs. sampling clock

6 Example: Switch References in PLL

7 What should I digitize?

8 SONET/SDH Clock Management
100% Redundancy is required at the line-card timing reference

9 Type-II PLL Phase Transient During Reference-switching
Dmax : maximum phase deviation d/dt : maximum phase step slope

10 Maximum Time Interval Error (MTIE)
Phase Offset (25.7ns max) slope < 81ns/1.326ms Frequency Offset (9.2ppm max) Typical LBW choice: 250Hz (clk rearrangement) ~ 1KHz( frequency translation)

11 “Hitless” Phase-Switching Architecture
t=t1, selA=1 / selB=0  fA- foffsetA,0 = fout,1, foffsetB,1 = fB t=t2, selA=0 / selB=1  fB- foffsetB,1 = fout,2, foffsetA,2 = fA  Dfout,1,2 = (fA-fB)-(foffsetA,0-foffsetB,1) = 0 if fA and fB ~ constant

12 Digital Implementation of Hitless Switching (1)
PLL LBW < 12KHz PFD SDADC fs = 311MHz

13 PFD ADC and Auto-zero Loop
“shift” the offset DAC value AZ bandwidth ~ 100KHz D avoids the DAC overflow Loop Bandwidth < 12KHz vs. SDADC fs = 311MHz  SNR > 22bits PFD full scale = 6.42ns  Offset DAC LSB ~ 100ps

14 What if Frequency Error Is Present?
<8FSPD Dfoffset,max =FSPD modulus (k=0~7) Dfout,1,2 = (fA-fB) - (foffsetA-foffsetB) – k  (0.5  2FSPD) 2FSPD: Phase Detector Full-scale (6.42ns)

15 Digital Implementation of Hitless Switching (2)
Each swallow: TD = 8Tvco

16 Phase Transient Measurement Setup
adjustable Df Linear phase detector “demodulates” the DUT output phase LOS (loss-of-signal) on clkB triggers the oscilloscope

17 Measured Phase Transient During Reference-switching
Wandering due to LOS Loop relocks the phase 116ps PD out residual Df = 35ps LOSB trigger the switching Initial Df = 180 (~25ns) LOSB Mode: Auto-switching (LOS triggers the switching)

18 Removing the External Loop Filter
DSP implementation replaces the bulky external loop filters (LF) Less Bill-of-Materials (BOM) Avoid excess noise-coupling at post-LF nodes

19 DSP-based Loop Filter Implementation
Gain ratio controls LBW and peaking No external loop filter components needed

20 PLL Bandwidth and Peaking Control
Feedforward (F) PFD ADC Integration (I) feedforward bits added Input bits accumulated varactor codes Reduced by SD (rounding) KF ~ LBW / (KPD x Kv) KI ~ (LBW)2 x (d-1) / (KPD x Kv) For Type-II PLL with low-peaking (d<0.1dB),

21 Connecting the Loop Filter to Varactors
2nd-order SD generates varactor cntl. voltage DAC expander reduces the analog hardware cost by 16x

22 VCO Varactor Implementation

23 Varactor DAC and Multiplexer
At any instant, only 8 varactors receive DAC tuning voltages

24 DAC Movement Across Sub-Varactor
Accumulator bits slowly move the DAC banks Feedforward bits vary the tuning voltage Vg

25 Chip Micrograph 3.5mm 5.1mm reference generator. output drivers
PFD/ADC B VCO divider 3.5mm digital routes / regulators PFD/ADC F varactor master regulator PFD/ADC A DAC expander multiplexer 5.1mm

26 Discrete Solution vs. Integrated Solution
50mm discrete solution hybrid solution 23mm 11mm presented solution No external loop filters are required. dramatically simplifies the line card design!

27 PLL Characteristics Measurement
10 100 1K 10K 100K 1M 10M Frequency (Hz) L(f) (dBc/Hz) -20 -40 -60 -80 -100 -120 -140 -160 Phase LBW=800Hz 622.08MHz Output -97dBc/Hz @10KHz -142dBc/Hz @1MHz Jitter Generation Frequency (Hz) 100 1K 10K -2 -4 -6 -8 -10 -12 -14 -16 Loop Transfer (dB) 800Hz 1600Hz 3200Hz 6400Hz Jitter Transfer 2 19.44Mhz Input 622.08MHz Output Measured integrated jitter: OC48 band  0.69ps OC192 band  0.26ps Measured peaking: < 0.1dB

28 Performance Summary 0.25m-CMOS 3.5mm by 5.1mm 11 X 11 CBGA 350mW
Technology 0.25m-CMOS Die Size 3.5mm by 5.1mm Package 11 X 11 CBGA Vdd=3.3V 350mW Supported PLL Bandwidth (LBW) 800Hz, 1600Hz, 3200Hz, 6400Hz Loop Transfer Peaking <0.1dB During Reference BW=800Hz Maximum Output Phase Step 200ps Maximum Output Phase Slope (MTIE: <61.08 ns/ms for 3/4E) 4.5 ns/ms Jitter BW=800Hz OC-48 band (12KHz ~ 20MHz) 0.8ps (WC) OC-192 band (50KHz ~ 80MHz) 0.4ps (WC)

29 Conclusion Digital “hitless” clock-switching is demonstrated, enabling the on-chip implementation for SONET/SDH clock management. Loop components are digitally implemented, which minimizes the external noise coupling and also has the good control over loop characteristics. Concise digital implementation of digital varactors simplifies the hardware implementation, and enhances the VCO performance, enabling the “jitter-cleaning” to the PLL input clocks.


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