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The World Leader in High-Performance Signal Processing Solutions 1. Theory (why & how it works) 2. Error Sources 3. Advanced DDS Capabilities 4. Applications Examples Direct Digital Synthesis Theory & Applications paul.smith@analog.com

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1 Phase Time 360 360t*F out TIME F out TIME 0 PHASE

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2 Discrete Phase Discrete Time PHASE TIME 2 n -1 0 F out

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3 How do you build this? PHASE TIME 2 n -1 0 n PHASE REGISTER CLOCK n PHASE ACCUMULATOR n 1 n = 24 - 48 BITS F clk

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4 Changing Frequency PHASE TIME 2 n -1 0 n PHASE REGISTER CLOCK n PHASE ACCUMULATOR n n = 24 - 48 BITS M FREQUENCY CONTROL M = TUNING WORD DELTA PHASE REGISTER M n M F clk

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5 Getting a Sinewave Output AMPLITUDE TIME 0 n PHASE REGISTER CLOCK n PHASE ACCUMULATOR n n = 24 - 48 BITS FREQUENCY CONTROL M = TUNING WORD DELTA PHASE REGISTER M n M F clk PHASE-TO AMPLITUDE CONVERTER p

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6 Signal Flow Through the DDS Architecture REFERENCE CLOCK PHASE ACCUMULATOR (n-BITS) PHASE-TO-AMPLITUDE CONVERTER DAC M TUNING WORD SPECIFIES OUTPUT FREQUENCY AS A FRACTION OF REFERENCE CLOCK FREQUENCY DIGITAL DOMAINANALOG N DDS CIRCUITRY (NCO) TO FILTER 2 n = F o M F clk F n

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7 Another Way to Look at DDS 6-bit phase wheel 0 1 2 3 4 63 … … 0 2 4 31 29 … … 5-bit amplitude resolution vector data raw DDS-DAC output filtered output compared output

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The World Leader in High-Performance Signal Processing Solutions 1. Theory (why & how it works) 2. Error Sources 3. Advanced DDS Capabilities 4. Applications Examples Direct Digital Synthesis Theory & Applications paul.smith@analog.com

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9 Errors in a DDS System PHASE ACCUMULATOR F clk n n FREQUENCY CONTROL M = TUNING WORD PHASE REGISTER DELTA PHASE REGISTER M CLOCK n n n PHASE TRUNCATION 12-19 BITS N-BITS (10-14) n = 24 - 48 BITS PHASE-TO AMPLITUDE CONVERTER SYSTEM CLOCK F out AMPLITUDE QUANTIZATION p M DAC ERRORS DAC

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10 Amplitude Errors Quantized waveform Sinewave Therefore there will be spectral components 6.02N + 1.76 quantization noise is only valid when clock and data are uncorrelated. NOT THE CASE for a DDS! DAC non-linearities INL and DNL spurs will alias Harmonics from the analog output stage will NOT alias

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11 Aliased Distortion Terms Freq Distortion in an analog system Freq Fs2Fs Distortion in an sampled system All the distortion terms show up in the passband

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12 Effects of Choosing an Odd Value For M PHASE TIME 2 n -1 0 M=4 PHASE TIME 2 n -1 0 M=5 30 31 28 29 27 30

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13 Effect Sampling Clock / Output Frequency Ratio on SFDR for Ideal 12-bit DAC (A) F OUT = 2.0000 MHz, f S = 80.0000 MHz FFT SIZE = 8192 THEORETICAL 12-BIT SNR = 74dB FFT PROCESS GAIN = 36dB = 10log(8192/2) FFT NOISE FLOOR = 110dBFS SFDR = 77dBc SFDR = 94dBc Ratio = 80/2 = 40 Ratio = 80/2.0117 = 103/4096 (B) F OUT = 2.0117 MHz, f S = 80.0000 MHz

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14 Phase Truncation Errors Green points (outer circle) show n=8 phase accumulator 256 phase steps M=6 in this illustration Red points (inner circle) show p=5 32 steps passed on the phase- amplitude converter 3 points get truncated, but the 1 st and 4 th do not As the phase moves around the circle, the error becomes periodic Phase error = Amplitude error Due to phase-amplitude converter Periodic phase error = periodic amplitude error = spectral component

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15 Phase Truncation Error (Time Domain) Not only is the error periodic, but it also has a ramp shape Therefore we expect the spectral components fall at a 1/m rate (m = harmonic number)

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16 Phase Truncation Error (Frequency Domain) However, since this is a phenomenon in the digital domain, these spurs will alias. The largest spur is approximately -6.02p dBc (e.g., -72 dBc for p=12)

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The World Leader in High-Performance Signal Processing Solutions 1. Theory (why & how it works) 2. Error Sources 3. Advanced DDS Capabilities 4. Applications Examples Direct Digital Synthesis Theory & Applications paul.smith@analog.com

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18 Additional DDS Capabilities Add Frequency Register Sweep Chirp RAM profiles Amplitude control IQ modulation Multi-DDS For arrays Phase offset/compensation Spurkiller

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19 Frequency Control n PHASE REGISTER CLOCK n PHASE ACCUMULATOR n n = 24 - 48 BITS FREQUENCY CONTROL M = TUNING WORD DELTA PHASE REGISTER M n F clk PHASE-TO AMPLITUDE CONVERTER p M PRE- PROGRAMMED FREQUENCY CONTROL or RAM TIME FREQUENCY

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20 Amplitude Control n PHASE REGISTER CLOCK n PHASE ACCUMULATOR n F clk PHASE-TO AMPLITUDE CONVERTER p M DAC AMPLITUDE REGISTER

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21 IQ Modulation The DDS is the LO for the Quadrature Modulator Everything is in the Digital Domain and can be made as perfect as necessary by adding more bits Upsampling gives the DDS room to move the signal around

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22 Multiple DDS Precise phase control allows use in beam forming systems Each DDS starts up in its own phase Phase offsets compensate for phase mismatch in analog reconstruction filters

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23 COS(X) FTW Frequency Accumulator Phase Offset 14 32 16 10 DAC DDS Channel for spur reduction DDS Channel for amplitude modulation DDS Channel for phase modulation Register SpurKiller Technology Use an auxiliary DDS channel to add in a signal at the same frequency and amplitude as the spur, but 180° out of phase with the highest spur… AD9911 DDS core

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24 AD9911 SpurKiller 500 MHz DDS Its all in the Digital Domain!

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25 The Results of Using SpurKiller Technology on a DDS Output Spur OUTPUT FREQUENCY = 166 MHz Fclk = 500 MSPS 500 kHz / DIVISION BEFORE AFTER

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The World Leader in High-Performance Signal Processing Solutions 1. Theory (why & how it works) 2. Error Sources 3. Advanced DDS Capabilities 4. Applications Examples Direct Digital Synthesis Theory & Applications paul.smith@analog.com

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27 Output Circuits R OUT I FS – I I I OUT R SET u I FS 2 - 20mA typical u R OUT > 100k u Output compliance voltage < ±1V for best performance u That is, the output can go below ground!

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28 Single Transformer Coupling LC FILTER MINI-CIRCUITS ADT1-1WT 1:1 R LOAD = 50 V LOAD = ± 0.333V I OUT 0 TO 20mA 20 TO 0mA ± 6.67mA CMOS DAC 50 +0.45dBm Note: The 100 differential primary driving impedance represents the best compromise between the effects of transformer impedance mismatch and DAC SNR performance.

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29 Dual Transformer Coupling Transmission Line Transformer in series with outputs to help cancel HD2 Dual Transformer design helps minimize imbalance caused by mis- matched signal coupling from primary to secondary windings. RF Transformer from Coilcraft (TTWB-1-B) shows better performance for IFs at 200-300 MHz CMOS DAC 50 50 Mini-Circuits ADTL1-12 Coilcraft TTWB-1-B TO 50 LOAD 20-1200MHz0.13-425MHz V LOAD = ± 0.333V +0.45dBm 0 TO 20mA 20 TO 0mA

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30 Differential DC Coupling Using a Dual-Supply Op Amp I OUT 0 TO 20mA 20 TO 0mA CMOS DAC AD8055 + – +5V –5V 25 0V TO +0.5V +0.5V TO 0V C FILTER 500 1000 ± 1V f 3dB = 1 2 50 C FILTER OR AD8021

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31 Differential DC Coupling Using a Single-Supply Op Amp I OUT 0 TO 20mA 20 TO 0mA CMOS DAC AD8061 + – +5V 25 0V TO +0.5V +0.5V TO 0V C FILTER 500 2k 1k ± 1V +2.5V +5V 2k f 3dB = 1 2 50 C FILTER

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32 High-Speed Buffered Differential DAC Outputs I OUT CMOS DAC + – AD813x ADA493x V OCM 2.49k 5V p-p DIFFERENTIAL OUTPUT 0 TO 20mA 20 TO 0mA 0V TO +0.5V +0.5V TO 0V 25 f 3dB = 1 2 50 C FILTER C FILTER 500

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33 Generating a Clock With a DDS External filtering removes unwanted images A squaring circuit converts the signal back to a digital clock

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34 Why You Need a Reconstruction Filter Fout = 56 MHz, Fclk = 175 MHz The MSB does not have a consistent pulse width Jitter shows up when unfiltered output is fed directly to a comparator

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35 AN-823 Discusses DDS-based Clocks With Very Low Phase Noise Phase noise floor below –150dBc/Hz Power dissipation <200mW per channel 15.1 MHz 40.1 MHz 75.1 MHz 100.3 MHz REF CLOCK = 500MHz, MULTIPLIER DISABLED 100.3 MHz 75.1 MHz 40.1 MHz 15.1 MHz

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36 AD9858 1GSPS DDS with Phase Detector and RF Mixer

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37 PLL General Architecture RF ÷N÷N Loop Filter VCO Phase/ Frequency Detector F ref refRF FNF

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38 DDS Used as PLL Reference RF ÷N÷N Loop Filter VCO Phase/ Frequency Detector F ref DDS n ref RF 2 F NMF M

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39 DDS Used in Fractional-N Loop RF Loop Filter VCO Phase/ Frequency Detector F ref DDS ref RF n 2 F M F M

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40 DDS Used in Translation Loop RF Loop Filter VCO Phase/ Frequency Detector F ref DDS ÷N÷N n 2 clk F M refRF FNF F clk

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41 RF Upconversion Using Analog IQ Mixing DSP CHANNEL FILTER TxDAC BPF PA RF LO I Q I Q 0° 90° TxDAC BPF AD977x ADL537x 300MHz – 3.8GHz

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42 RF Upconversion Using Digital IQ Mixing DSP CHANNEL FILTER DAC BPF PA RF I Q I Q 0° 90° N N BPF NCO QDUC = QUADRATURE DIGITAL UPCONVERTER AD9857 AD9957 IF TO 400MHz (AD9957) LO

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43 RF Upconversion Using Dual DDS for LO DSP CHANNEL FILTER TxDAC BPF PA RF I Q I Q 0° 90° TxDAC BPF AD977x ADL5385 50MHz - 2.2GHz DUAL DDS

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44 On-Line DDS Tools ADIsimDDS

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45 DDS Design Tool Main Screen

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46 DDS Design Tool: Tabular Display of Spurs

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47 DDS Design Tool: Display Options and Filter Selection

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48 http://www.analog.com/dds Click More … to find the cool technical papers

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49 Summary DDS can be used to obtain a variety of precision waveforms Compared to other frequency generating techniques, a DDS has the following advantages: Precise phase control without affecting frequency Precise frequency control without affecting phase Fast arbitrary phase changes Fast arbitrary frequency changes Precision modulation DDS has well known error characteristics Care must be taken designing the output analog circuitry Applications abound! ADI makes some GREAT parts

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