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**Chapter 3 Gate-Level Minimization**

The Boolean functions also can be simplified by map method as Karnaugh map or K-map. The map is made up of squares, with each square representing one minterm of the function. This produces a circuit diagram with a minimum number of gates and the minimum number of inputs to the gate. It is sometimes possible to find two or more expressions that satisfy the minimization criteria.

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Two-Variable map Two-variable has four minterms, and consists of four squares. m1 + m2 + m3 = x’y + xy’ + xy = x + y

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**Three-Variable map m5+m7= xy’z + xyz = xz(y’ + y) = xz**

Note that the minterms are not arranged in a binary sequence, but similar to the Gray code. For simplifying Boolean functions, we must recognize the basic property possessed by adjacent squares. m5+m7= xy’z + xyz = xz(y’ + y) = xz cancel y

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**Simplification of the number of adjacent squares**

A larger number of adjacent squares are combined, we obtain a product term with fewer literals. 1 square = 1 minterm = three literals. 2 adjacent squares = 1 term = two literals. 4 adjacent squares = 1 term = one literal. 8 adjacent squares encompass the entire map and produce a function that is always equal to 1. It is obviously to know the number of adjacent squares is combined in a power of two such as 1,2,4, and 8.

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Example Ex. 3-3 F(x, y, z) = ∑(0, 2, 4, 5, 6) F = z’ + xy’

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**3-2. Four-variable map 1 square = 1 minterm = 4 literals**

2 adjacent squares = 1 term = 3 literals 4 adjacent squares = 1 term = 2 literals 8 adjacent squares = 1 term = 1 literal 16 adjacent squares = 1

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**Example Ex. 3-6 F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’ = B’D’ + B’C’ +**

A’CD’

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**Essential prime implicants**

If a minterm in a square is covered by only one prime implicant, that the prime implicant is said to be essential.

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Prime implicant A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map. This shows all possible ways that the three minterms(m3,m9,m11) can be covered with prime implicants. F = BD+B’D’+CD+AD = BD+B’D’+CD+AB’ = BD+B’D’+B’C+AD = BD+B’D’+B’C+AB’

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3-3. Five-variable map Fig.3-12, the left-hand four-variable map represents the 16 squares where A=0, and the other four-variable map represents the squares where A=1. In addition, each square in the A=0 map is adjacent to the corresponding square in the A=1 map.

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Five-variable map It is possible to show that any 2k adjacent squares, for k=(0,1,2,…,n) in an n-variable map, will represent an area that gives a term of n−k literals(n>k). When n=k, it is identity function.

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example Ex. 3-7 F(A, B, C, D, E) = (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31) Because of both parts of the map have the common term (A’BD’E+ABD’E) so the sum of products is F = A’B’E’ + BD’E + ACE common

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**3-4. Product of sums simplification**

If we mark the empty squares by 0’s rather than 1’s and combine them into valid adjacent squares, we obtain the complement of the function, F’. Use the DeMorgan’s theorem, we can get the product of sums. Ex.3-8 Simplify the Boolean function in (a) sum of products (b) product of sums F(A, B, C, D) = ∑(0, 1, 2, 5, 8, 9, 10)

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**Example (a) SOPs F= (b) POSs F’= By DeMorgan’s thm B’D’ + B’C’ + A’C’D**

AB + CD + BD’ (A’+B’) .(C’+D’) .(B’+D)

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Gate implementation

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**Exchange minterm and maxterm**

Consider the truth table that defines the function F in Table 3-2. Sum of minterms F(x, y, z) = ∑(1, 3, 4, 6) Product of maxterms F(x, y, z) = ∏(0, 2, 5, 7) In the other words, the 1’s of the function represent the minterms, and the 0’s represent the maxterms.

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**3-5. Don’t care conditions**

Ex.3-9 Simplify the F (w, x, y, z)= ∑(1, 3, 7, 11, 15) with don’t-care conditions d(w, x, y, z) = ∑(0, 2, 5) In part (a) with minterms 0 and 2 F = yz + w’x’ In part (b) with minterm 5 F = yz + w’z

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**3-6. NAND and NOR implementation**

NAND gate is a universal gate because any digital system can be implemented with it. NAND gate can be used to express the basic gates, NOT, AND, and OR.

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**Two graphic symbols for NAND gate**

In part (b), we can place a bubble (NOT) in each input and apply the DeMorgan’s theorem, then get a Boolean function in NAND type.

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**Two-level implementation**

Double complementation, so can be removed F = AB + CD = = OR gate,Fig.3-18

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**Multilevel NAND circuits**

To convert a multilevel AND-OR diagram into an all-NAND diagram using mixed notation is as follows: Convert all AND gates to NAND gates with AND-invert graphic symbols. Convert all OR gates to NAND gates with invert-OR graphic symbols. Check all the bubbles in the diagram. For every bubble that is not compensated by another small circle along the same line, insert an inverter or complement the input literal.

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**Multilevel NAND circuits**

, ,

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NOR implementation The NOR operation is the dual of the NAND operation, all procedures and rules for NOR logic are the dual of NAND logic. NOR gate is also a universal gate.

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**Two graphic symbols for NOR gate**

In part (b), we can place a bubble (NOT) in each input and apply the DeMorgan’s theorem, then get a Boolean function in NOR type.

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**Implementing F with NOR gates**

F = (AB’ + A’B)(C + D’) To compensate for the bubbles in four inputs, it is necessary to complement the corresponding input literals.

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**3-7. Other two-level implementations**

Some NAND or NOR gates allow the possibility of a wire connection between the outputs of two gates to provide a wired logic. Open-collector TTL NAND gates, when tied together, perform the wired-AND logic (Fig.3-28). The wired-AND gate is not a physical gate. Wired-And

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Nondegenerate forms We consider four types of gates: AND, OR, NAND, and NOR. These will have 16 combinations of two-level forms. Eight of these combinations are said to be degenerate forms, because they degenerate to a single operation. The other eight nondegenerate forms produce an SOPs or POSs as follows: AND-OR 3-4 OR-AND 3-4 NAND-NAND 3-6 NOR-NOR 3-6 NOR-OR NAND-AND OR-NAND AND-NOR

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**AND-OR-INVERT implementation**

The two forms NAND-AND and AND-NOR are equivalent forms and can be treated together. F = (AB + CD + E)’ Shift back

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**OR-AND-INVERT implementation**

The OR-NAND form resembles the OR-AND form, except for the inversion done by the bubble in the NAND gate. F = [(A + B)(C + D)E]’ Shift back

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**Tabular summary and example**

Because of the INVERT part in each case, it is convenient to use the simplification of F’ of the function.

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Example Ex.3-11 Implement the function of Fig.3-31(a) with the four two-level forms listed in Table 3-3. The complement of the function by combining the 0’s: F’ = x’y + xy’ + z The normal output for this function F = (x’y + x’y + z)’ Which is in the AND-OR-INVERT form.

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Example The AND-NOR and NAND-AND implementations are shown as follows.

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Example The OR-AND-INVERT forms require a simplified expression of the complement of the function in POSs. Combine the 1’s in the map F = x’y’z’ + xyz’ Complement of the function F’ = (x + y + z)(x’ + y’ + z)

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**Example The normal output F F = (x + y + z)(x’ + y’ + z)]’**

We can implement the function in the OR-NAND and NOR-OR forms as follows.

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**3-8. Exclusive-OR function**

The XOR symbol denote as ⊕, the Boolean operation: x ⊕ y = xy’ + x’y The X-NOR symbol denote as ⊙, the Boolean operation: x ⊙ y = (x ⊕ y )’ = xy + x’y’ The identities of the XOR operation: x ⊕ 0 = x x ⊕ 1 = x’ x ⊕ x = 0 x ⊕ x’ = 1 x ⊕ y’ = x’ ⊕ y = (x ⊕ y)’ Commutative and associative: A ⊕ B = B ⊕ A (A ⊕ B) ⊕ C = A ⊕ (B ⊕ C) = A ⊕ B ⊕ C

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**Exclusive-OR implementations**

Fig.3-32(b), the first NAND gate performs the operation (xy)’ = (x’ + y’). (x’ + y’)x + (x’ + y’)y = xy’ + x’y = x ⊕ y

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**Odd function Boolean expression of three-variable of the XOR:**

A ⊕ B ⊕ C = (AB’ + A’B)C’ + (AB + A’B’)C = AB’C’ + A’BC’ + ABC + A’B’C =∑(1, 2, 4, 7) Odd function defined as the logical sum of the 2n/2 minterms whose binary numerical values have an odd number of 1’s.

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Odd and Even functions The 3-input odd function is implemented by means of 2-input exclusive-OR gates.

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**Parity generation and checking**

Table 3-4, the P make the total number of 1’s even(including P). P constitutes an odd function. A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even. P=x ⊕ y ⊕ z

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**Parity generation and checking**

The circuit that generates the parity bit in the transmitter(receiver) is called a parity generator(checker). Transmitter Receiver

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Example of even parity Since the information was transmitted with even parity, the four bits received must have an even number of 1’s. An error occurs during the transmission if the four bits received have an odd number of 1’s. The output of the parity checker, denoted by C, will be equal to 1 if an error occurs, that is, if the four bits received have an odd number of 1’s. C = x ⊕ y ⊕ z ⊕ P Error

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**3-9. Hardware Description Language (HDL)**

It resembles a programming language, but is specifically oriented to describing hardware structures and behavior. There are two applications of HDL processing: Logic simulation: allows the detection of functional errors in a design without having to physically create the circuit. Logic synthesis: the process of deriving a list of components and their interconnections (called a netlist) from the model of a digital system described in HDL.

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**Module representation**

Identifiers must start with an alphabetic character or an underscore. HDL Example 3-1 //Description of simple circuit Fig. 3-37 Module smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e; and g1(e,A,B); not g2(y,C); or g3(x,e,y); endmodule keywords

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Gate delays The delay is specified in terms of time units and the symbol #. ‘timescale 1ns/100ps The first number specifies the unit of measurement for time delays. The second number specifies the precision for which the delays are rounded-off. If no timescale is specified, the simulator defaults to a certain time unit, usually 1 ns.

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Gate delays

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**Stimulus and circuit description modules**

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Boolean expressions Boolean expressions are specified in Verilog HDL with a continuous assignment statement consisting of the keyword assign followed by a Boolean expression. assign x = (A & B) ∣ ~ C ;

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**User-Defined primitives (UDP)**

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**User-Defined primitives (UDP)**

With keywords and, or, etc…,are referred to as system primitives. The user can create additional primitives by defining them in a tabular form, so-called UDP. UDP use the keyword “primitive” instead of keyword “module”. HDL proceeds according to the following rules: It is declared with the keyword primitive followed by a name and port list. There can be only one output and it must be listed first in the ort list and declared with an output keyword.

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**User-Defined primitives (UDP)**

There can be any number of inputs. The order in which they are listed in the input declaration must conform to the order in which they are given values in the table that follows. The truth table is enclosed within the keywords table and endtable. The values of the inputs are listed in order ending with a colon(:). The output is always the last entry in a row followed by a semicolon(;). It ends with the keyword endprimitive.

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Gate-Level Minimization Chapter 3. Digital Circuits 2 3-1 The Map Method The complexity of the digital logic gates the complexity of the algebraic expression.

Gate-Level Minimization Chapter 3. Digital Circuits 2 3-1 The Map Method The complexity of the digital logic gates the complexity of the algebraic expression.

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