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Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 1 Digital Fundamentals.

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Presentation on theme: "Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Slide 1 Digital Fundamentals."— Presentation transcript:

1 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 1 Digital Fundamentals CHAPTER 3 Logic Gates

2 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 2 Logic Gates InverterInverter AND GateAND Gate OR GateOR Gate Exclusive-OR GateExclusive-OR Gate NAND GateNAND Gate NOR GateNOR Gate Exclusive-NOR GateExclusive-NOR Gate

3 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 3 The Inverter

4 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 4 The Inverter Boolean expressionTruth table 0 = LOW 1 = HIGH Pulsed waveforms The output of an inverter is always the complement (opposite) of the input.

5 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 5 The AND Gate The AND Gate

6 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 6 The AND Gate The AND Gate Boolean expression Truth table 0 = LOW 1 = HIGH Pulsed waveforms The output of an AND gate is HIGH only when all inputs are HIGH.

7 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 7 The AND Gate The AND Gate 3-Input AND Gate 4-Input AND Gate

8 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 8 The OR Gate

9 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 9 The OR Gate Boolean expression Truth table 0 = LOW 1 = HIGH The output of an OR gate is HIGH whenever one or more inputs are HIGH Pulsed waveforms

10 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 10 The OR Gate 3-Input OR Gate 4-Input OR Gate

11 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 11 The NAND Gate

12 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 12 The NAND Gate Boolean expression Truth table 0 = LOW 1 = HIGH The output of a NAND gate is HIGH whenever one or more inputs are LOW. Pulsed waveforms

13 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 13 The NAND Gate 3-Input NAND Gate 4-Input NAND Gate

14 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 14 The NOR Gate

15 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 15 The NOR Gate Boolean expression Truth table 0 = LOW 1 = HIGH The output of a NOR gate is LOW whenever one or more inputs are HIGH. Pulsed waveforms

16 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 16 The NOR Gate 3-Input NOR Gate 4-Input NOR Gate

17 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 17 Exclusive-OR and Exclusive-NOR Gates

18 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 18 Exclusive-OR Gate Boolean expression Truth table 0 = LOW 1 = HIGH The output of an XOR gate is HIGH whenever the two inputs are different. Pulsed waveforms

19 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 19 Exclusive-NOR Gate Boolean expression Truth table 0 = LOW 1 = HIGH The output of an XNOR gate is HIGH whenever the two inputs are identical. Pulsed waveforms

20 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 20 Programmable Logic

21 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 21 Programmable Logic Programmable AND arrayProgrammable AND array Programmable link technologyProgrammable link technology Device programmingDevice programming In-system programming (ISP)In-system programming (ISP)

22 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 22 Programmable Logic Programmable AND arrayProgrammable AND array

23 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 23 Programmable Logic Programmable link technology Fuse technologyFuse technology Anti-fuse technologyAnti-fuse technology EPROM technologyEPROM technology EEPROM technologyEEPROM technology SRAM technologySRAM technology

24 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 24 Programmable Logic Device programming Design entryDesign entry –Text entry –Graphic (schematic) entry

25 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 25 Programmable Logic In-system programming (ISP)In-system programming (ISP) –Joint Test Action Group (JTAG) –Imbedded processor

26 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 26 Fixed-Function Logic

27 Floyd Digital Fundamentals, 9/e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Slide 27 Fixed-Function Logic CMOSCMOS TTLTTL


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