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ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices XOR, Parity Circuits, Comparators

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2 Exclusive OR and Exclusive NOR Gates XOR : XNOR : Truth Table : XOR X Y XOR XNOR 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1 XOR X Y F X Y F

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3 XOR and XNOR Symbols Equivalent Symbols of XOR gate Equivalent Symbols of XNOR gate Any 2 signals (inputs or outputs) may be complemented without changing the resulting logic function

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4 SSI XOR and XNOR 74x86 : 4 XOR gates 74x266: 4 XNOR gates with “open collector” or “open drain” output

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5 XOR Application: Parity Circuit Odd Parity Circuit : The output is 1 if odd number of inputs are 1 Even Parity Circuit : The output is 1 if even number of inputs are 1 Example : 4-bit Parity Circuit Daisy-Chain Structure Tree structure Input : 1101 Odd Parity output : 1 Even Parity output : 0 I0 I1 I2 I3 ODD EVEN I0 I1 I2 I3 ODD EVEN

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6 MSI Parity Circuit : 74x280

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7 Parity-Checking Application: memory

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8 Comparators Compares Two binary words and indicate if they are equal Magnitude Comparators : A Comparator A=B? B A Comparator A=B B A>B A**
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9 Equality Comparators 1-bit comparator 4-bit comparator EQ_L

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10 Iterative Comparator

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11 Multi-bit Iterative Comparator

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12 MSI Comparator : 74x85 4 bit comparator 3 outputs : A=B, A B 3 Cascading inputs Functional Output equations : (A>B OUT)= (A>B)+(A=B).(A>B IN) (A**B IN) =0 (A BIN A**

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13 8 bit Comparator B0 A1 B1 A2 B2 A3 A0 B3 74x85 A**B Most Significant bitsLeast Significant bits
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14 8-bit Magnitude Comparator

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15 Other conditions

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16 Next… Adders, subtractors, ALUs Reading Wakerly CH-6.10-6.11

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Combinational Logic Design

Combinational Logic Design

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