Download presentation

Presentation is loading. Please wait.

Published byMalcolm Anstey Modified over 2 years ago

1
University of Toronto Minimization of Delay Sensitivity to Process Induced Vth Variations Georges Nabaa Farid N. Najm University of Toronto

2
Nabaa-NajmNEWCAS-052 Outline n Introduction n Problem formulation and goals n Methodology n Standard simulations l Static gates l Dynamic gates l Transmission gates n Standalone simulations n Sizing simulations n Conclusion

3
Nabaa-NajmNEWCAS-053 Introduction n The threshold voltage is a fundamental operational parameter of a MOSFET n For the past 30 years, performance improvements in semiconductors have been achieved by decreasing channel length n This decrease had to be accompanied by a l Decrease supply voltage l Decrease threshold voltage (Vth) n This Vth decrease has not been followed by a corresponding decrease in threshold voltage variations

4
Nabaa-Najm Random Dopant Fluctuations n Threshold Voltage is a function of the dopants in the channel n Due to the decrease in the number of dopants in DSM processes there is increased variability IBM: ISSCC 2004

5
Nabaa-NajmNEWCAS-055 Threshold Voltage Variations n Threshold voltage variations (δ Vth ) cause variations in circuit delay that impact the chip timing yield l Can cause up to 30% variation in chip frequency [BKN02] n Threshold Variations can be divided into l Within-die l Die-to-die Tschanz 2002

6
Nabaa-NajmNEWCAS-056 Problem Formuation n Previous work applies chip wide compensation schemes l Unsuitable for the within-die component l Within-die variations become larger as the feature length gets smaller n We study design techniques that minimize the effects of threshold variations on circuit delay variability (minimize delay sensitivity) n Specifically, we explore: l Topology issues, e.g., series vs. parallel arrangements l Design style, e.g., static vs. dynamic (NAND vs NOR) l Optimization issues, e.g., sizing

7
Nabaa-NajmNEWCAS-057 Goals n Evaluate these styles based on performance penalty, area overhead, and delay variability minimization n This per gate approach tackles within-die variations intrinsically n Design δ Vth aware Libraries

8
Nabaa-NajmNEWCAS-058 Methodology n We model Vth variations (δ Vth ) as normally distributed random variables (RVs) l The 3σ limits of the Normals are from the technology files l Adjusted using the Law of Area: (Horstmann99) l The larger the transistors, the smaller the input Vth variations n For all the transistors in a given logic gate consider δ Vth variations as: l Independent Normals (n transistors -> n independent normals) l Fully Positively Correlated Normals

9
Nabaa-NajmNEWCAS-059 Methodology (cont) n Used 0.13um UMC process n Generated 1000 sweep points and link it to the DELVTO parameter in SPICE n Run the simulation and record propagation delay l Absolute delay is input dependent l For each gate we choose the worst-case input vectors

10
Nabaa-NajmNEWCAS-0510 Methodology n Assume Linearity between process and delay n From each sweep, the sensitivity is recorded as:

11
Nabaa-NajmNEWCAS-0511 Static Gates: Series better than Parallel n Series stacks exhibit less delay sensitivity than their parallel counterparts. l Explanation: body-effect minimizes the impact of V th l Design: insert series transistors to create series stacks

12
Nabaa-NajmNEWCAS-0512 Hybrid Gates n The fact that series are better than parallel led us to insert a serializing dummy transistor into the structure of a gate n For a 2-input NAND gate, two potential configurations: Configuration 1 Configuration 2 Standard

13
Nabaa-NajmNEWCAS-0513 Hybrid gates: Independent n Hybrid gates exhibit less delay variability than standard gates

14
Nabaa-NajmNEWCAS-0514 Hybrid Gates: Correlation n n Even with correlation l l Hybrid gates exhibit less delay variability than standard gates

15
Nabaa-NajmNEWCAS-0515 Hybrid Gates: Limitations n These gains come at the expense of larger absolute delays. n These delays can be recovered by a corresponding increase in area: l In order for the hybrid NAND to match the nominal delay performance its area must be 2.1 times the area of a standard NAND gate n This overhead is reduced as the number of inputs increases; l For a three input hybrid NAND, the area overhead required to match the nominal performance of a standard 3 input NAND gate is 1.5×. n To further minimize area overhead, we use a low V th for the dummy transistor. l Area overhead required to match similar performance is down to 78 %

16
Nabaa-NajmNEWCAS-0516 Dynamic Logic n Performed similar experiments on dynamic gates n NOR gates l Very susceptible to variations l The footer in standard dynamic logic helps to reduce variability l Still has large variability

17
Nabaa-NajmNEWCAS-0517 Dynamic Gates: NAND n NAND Dynamic gates exhibit less variation than NOR Dynamic Gates l Dynamic NAND has more variations than Static NAND n But footerless dynamic NAND gates are better than those with footer l Can be attributed to the fact that the footer transistor is also subjected to the normal δ Vth (and the circuit is already in series) n Use NAND Logic instead of NOR logic whenever possible. l Footerless NAND logic is fastest and less prone to variability

18
Nabaa-NajmNEWCAS-0518 Transmission gates n Transmission gates display the best delay variability robustness in both l Correlated simulations l Independent simulations n Can be explained through the intrinsic structure of the gate l NMOS and PMOS have opposite V th values (in sign) l In correlated simulations, when subjected to similar ΔVth, the contribution (faster or slower) that results from say the NMOS device is counterbalanced by an equal contribution from the PMOS device and vice versa. l In independent simulations, the variability still remains low (half that of a NAND gate)

19
Nabaa-NajmNEWCAS-0519 Transmission Gates Transmission Gate AND vs Static NAND (Independent) (Correlated)

20
Nabaa-NajmNEWCAS-0520 Standalone tests n Second Type of Test l Input threshold voltage variations on only one transistor at a time: n Goals: Find (if any) the critical transistor in a gate l Can be made wider to minimize the V th variations l Can be used in the context of a multiple V th solution n Results: l Bottommost transistor of a stack constitutes the bottleneck l This transistor can be made larger to minimize variability l Can also be used in the context of a multiple V th solution

21
Nabaa-NajmNEWCAS-0521 Sizing n Third set of tests l Simulated gates with different transistor sizes n The sizing simulations show that: l Larger gates demonstrate less variability l Optimal widths are twice the width of standard gates

22
Nabaa-NajmNEWCAS-0522 Sizing

23
Nabaa-NajmNEWCAS-0523 Conclusion n We studied the delay sensitivity of major design families with respect to Vth variations n Series stack are less sensitive than parallel configurations n Serialized standard gates: hybrid NAND and NOR gates n NAND footerless logic is better than standard dynamic logic. n Transmission gates are intrinsically robust with respect to V th variations n Optimal sizing of gates seems around 2x that of standard gates

Similar presentations

© 2016 SlidePlayer.com Inc.

All rights reserved.

Ads by Google