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CS1104 – Computer Organization Aaron Tan Tuck Choy School of Computing National University of Singapore

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CS Lecture 10: Combinational Circuits: Programmable Logic Devices 2 Lecture 10: Combinational Circuits Programmable Logic Devices Programmable Logic Devices PN Diode Operation AND Logic Arrays OR Logic Arrays Two-level AND-OR Arrays Programmable Logic Array (PLA) Realising Logic Functions with PLAs

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CS Lecture 10: Combinational Circuits: Programmable Logic Devices 3 Lecture 10: Combinational Circuits Programmable Logic Devices Read-Only Memory (ROM) Programmable Read-Only Memory (PROM) Realising Logic Functions with PROMs Progammable Array Logic (PAL) Realising Logic Functions with PALs

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CS Programmable Logic Devices4 Programmable Logic Devices (PLDs) are IC chips with internal logic gates connected by electronic fuses. These fuses can be blown (by programming) to obtain different circuit configurations. Semi-customized chips that give high packing density at reasonable cost. Three classes of PLDs are : Programmable Logic Array (PLA) Programmable Read Only Memory (PROM) Programmable Array Logic (PAL)

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CS Programmable Logic Devices5 Fixed AND array Fused programmable OR array Fuses InputsOutputs Fixed OR array Fused programmable AND array Fuses InputsOutputsInputs Fused programmable OR array Fuses Outputs FusesFused programmable AND array Programmable Read Only Memory (PROM) Programmable Array Logic (PAL) Programmable Logic Array (PLA)

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CS Programmable Logic Devices6 Programming an array – blowing the fuses. AA'BB' x1x1 x2x2 x3x3 AA'BB' x 1 = A.B x 2 = A'.B x 3 = A.B' (a) Unprogrammed(b) Programmed Example of a basic AND array

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CS Programmable Logic Devices7 PLDs use diodes. A PN diode is an electronic device formed by creating a junction of two types of semi- conductor materials, p type and n type. Forward-biased: When p side (anode) is more positive than n side (cathode), it behaves as a closed switch. Reverse-biased: When cathode is more positive than anode, it behaves as an open circuit. PN AnodeCathode PN junction diode and schematic symbol. Forward-biased (closed circuit) Reverse-biased (open circuit)

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CS PN Diode Operation8 AB +V A=1B=1 +V A=0B=0 +V (a) (b) (c) (a) With pull-up resistor. (b) Reverse-biased: diode open; B pulled up to 1. (c) Forward-biased: diode shorted, forcing B to 0. (d) With pull-down resistor. (e) Reverse-biased: diode open; B pulled down to 0. (f) Forward-biased: diode shorted, forcing B to 1. PN diode operation for digital applications. AB A=0B=0 A=1B=1 (d) (e) (f)

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CS AND Logic Arrays9 (a) (b) A f(A,B,C) = A.B.C +V B C A=1 f(A,B,C) = 1 +V B=1 C=1 A=0 f(A,B,C) = 0 +V B=1 C=1 A=0 f(A,B,C) = 0 +V B=0 C=1 (c) (d) (a) Basic configuration. (b) All diodes open; f pulled up to 1. AND function realised with a diode array. (c) One diode shorted, forcing f to 0. (d) Multiple diodes shorted, forcing f to 0.

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CS OR Logic Arrays10 OR Logic Arrays A f(A,B,C) = A+B+C B C A=0 f(A,B,C) = 0 B=0 C=0 A=1 f(A,B,C) = 1 B=0 C=0 (a) (b) (c) OR function realised with a diode array. (a) Basic configuration. (b) All diodes open; f pulled up to 0. (c) One diode shorted, forcing f to 1.

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CS Two-level AND-OR Arrays11 Two-level AND-OR Arrays AND and OR circuits can be interconnected to realise any arbitrary switching function. Example: f(a,b,c)=a.b.c'+b'.c

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CS Programmable Logic Array (PLA)12 Programmable Logic Array (PLA) Combination of a programmable AND array followed by a programmable OR array. Example: Design a PLA to realise the following three logic functions and show the internal connections. f 1 (A,B,C,D,E) = A'.B'.D' + B'.C.D' + A'.B.C.D.E' f 2 (A,B,C,D,E) = A'.B.E + B'.C.D'.E f 3 (A,B,C,D,E) = A'.B'.D' + B'.C'.D'.E + A'.B.C.D

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CS Realising Logic Functions with PLAs 13 Realising Logic Functions with PLAs f 1 (A,B,C,D,E) = A'.B'.D' + B'.C.D' + A'.B.C.D.E' f 2 (A,B,C,D,E) = A'.B.E + B'.C.D'.E f 3 (A,B,C,D,E) = A'.B'.D' + B'.C'.D'.E + A'.B.C.D A B C D E P1P1 P3P3 P4P4 P6P6 P5P5 P2P2 P7P7 Programmable OR array Programmable AND array A'B'D' X X X B'CD' X X X X X X X X A'BCDE' A'BE X X X X X X X B'CD'E B'C'D'E X X X X A'BCD X X X X f1f2f3f1f2f3 XXX XX XXX A'.B'.D'B'.C.D'A'.B.C.D.E'

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CS Read-Only Memory (ROM)14 Read-Only Memory (ROM) A semi-conductor memory is a device where data can be stored and retrieved. Logically, this memory device can be regarded as a table of memory cells (data). 0123::::n0123::::n Addresses 1-word data 1-bit data :::: word size

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CS Read-Only Memory (ROM)15 Read-Only Memory (ROM) A Read-Only Memory (ROM) is a memory device where data are read from, but not written to. Writing is done at time of customisation, or, by special programming devices (programmable ROM). Any Boolean expression can be implemented using ROM. Procedure: Obtain a truth table, treat the inputs as addresses and outputs as data. Advantage: Boolean functions directly implemented. Disadvantages: Dont care conditions not used, and limited input variables (e.g. 10 inputs – 1K, 16 inputs – 64K, 20 inputs – 1M).

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CS Read-Only Memory (ROM)16 Read-Only Memory (ROM) Different types of ROM devices available: ROM: Read-Only Memory Data written into memory by mask programming during manufacturing time. Expensive start-up cost but economical for high volume. Cannot be erased after data are programmed in. PROM: Programmable ROM Semi-custom chip. Fuses can be broken by special hardware programmer unit. Cost-effective for low volumes. Cannot be erased after programming.

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CS Read-Only Memory (ROM)17 Read-Only Memory (ROM) EPROM: Erasable PROM Similar to PROM except that data can be completely erased by exposure to ultra-violet light. EEPROM: Electrically Erasable PROM A PROM where data can be selectively erased by hardware programmer unit, rather than by ultra-violet light. Useful for remote devices which can be re-programmed from a distance.

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CS Programmable Read-Only Memory (PROM) 18 Programmable Read-Only Memory (PROM) Devices with fixed AND array (which is a decoder) and programmable OR array. The AND array (decoder) generates all 2 n possible minterm products of its n inputs (often referred to as n-to-2 n decoder). n input lines, m output lines. Bit combination of input variables – address. Bit combination of output lines – word (each word contains m bits).

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CS Programmable Read-Only Memory (PROM) 19 Programmable Read-Only Memory (PROM) I0I0 I1I1 I2I2 m0m0 m2m2 m3m3 m5m5 m4m4 m1m1 m7m7 Programmable OR array Fixed AND array X X XX X X X XX X XXXX X O1O2OkO1O2Ok X X X X X X X X X m6m Minterms Programmable read-only memory (PROM) can realize K functions f(I 2,I 1,I 0 ).

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CS Programmable Read-Only Memory (PROM) 20 Programmable Read-Only Memory (PROM) 2 n x m ROM => 2 n words, each word m bits => 2 n x m bits 2 n x m ROM n inputs m outputs

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CS Programmable Read-Only Memory (PROM) 21 Programmable Read-Only Memory (PROM) Logic construction of a 32 x 4 ROM.

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CS Realising Logic Functions with PROMs 22 Realising Logic Functions with PROMs Example (8 x 3 ROM): f 1 (A,B,C) = A.B + B'.C f 2 (A,B,C) = (A+B'+C).(A'+B) f 3 (A,B,C) = A + B.C First, we convert each function to canonical SOP form. f 1 (A,B,C) = A.B + B'.C = A.B.C' + A.B.C + A'.B'.C + A.B'.C = m(1,5,6,7) f 2 (A,B,C) = (A+B'+C).(A'+B) = (A+B'+B).(A'+B+C').(A'+B+C) = M(2,4,5) = m(0,1,3,6,7) f 3 (A,B,C) = A + B.C = A.B'.C' + A.B'.C + A.B.C' + A.B.C + A'.B.C = m(3,4,5,6,7)

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CS Realising Logic Functions with PROMs 23 Realising Logic Functions with PROMs C B A m0m0 m2m2 m3m3 m5m5 m4m4 m1m1 m7m7 Programmable OR array Fixed AND array X X XX X X X XX X XXXX X f 1 = m(1,5,6,7) f 2 = m(0,1,3,6,7) f 3 = m(3,4,5,6,7) X X X X X X X X X m6m6 Minterms XXXX XXXX XXXX X X

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CS Realising Logic Functions with PROMs 24 Realising Logic Functions with PROMs 0: : : : : : : : x 3 ROM

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CS Programmable Array Logic (PAL)25 Programmable Array Logic (PAL) Introduced in late 1970s by Monolithic Memories Inc. as lower cost replacement for logic gates, PROMs, and PLAs. PAL has programmable AND array and fixed OR array. Less general than PLA but easier to manufacture and design. Product terms belong to different OR gates, cannot be shared.

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CS Programmable Array Logic (PAL)26 Programmable Array Logic (PAL) CBAD P1P1 P2P2 P3P3 O1O1 P4P4 P5P5 P6P6 O2O2 Programmable AND array Fixed OR array

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CS Realising Logic Functions with PALs 27 Realising Logic Functions with PALs Procedure is to obtain minimal SOP expressions. Example: f (A,B,C,D) = A'.B'.D' + B'.C.D' + A'.B.C.D f (A,B,C,D) = A'.B + B'.C.D' f (A,B,C,D) = A'.B'.D' + B'.C'.D' + A'.B.C.D

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CS Realising Logic Functions with PALs 28 Realising Logic Functions with PALs PAL realisation of f a, f ß and f r. A P1P1 P2P2 P3P3 f P4P4 P5P5 P6P6 f P4P4 P5P5 P6P6 f BCD xxx xxx xxx xxx xxxx xxxx xx xxx xxxxxxxx f (A,B,C,D) = A'.B'.D' + B'.C.D' + A'.B.C.D f (A,B,C,D) = A'.B + B'.C.D' f (A,B,C,D) = A'.B'.D' + B'.C'.D' + A'.B.C.D

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