Download presentation

Presentation is loading. Please wait.

1
**CS1104 – Computer Organization http://www.comp.nus.edu.sg/~cs1104**

Aaron Tan Tuck Choy School of Computing National University of Singapore

2
**Lecture 10: Combinational Circuits Programmable Logic Devices**

PN Diode Operation AND Logic Arrays OR Logic Arrays Two-level AND-OR Arrays Programmable Logic Array (PLA) Realising Logic Functions with PLAs CS Lecture 10: Combinational Circuits: Programmable Logic Devices

3
**Lecture 10: Combinational Circuits Programmable Logic Devices**

Read-Only Memory (ROM) Programmable Read-Only Memory (PROM) Realising Logic Functions with PROMs Progammable Array Logic (PAL) Realising Logic Functions with PALs CS Lecture 10: Combinational Circuits: Programmable Logic Devices

4
**Programmable Logic Devices**

Programmable Logic Devices (PLDs) are IC chips with internal logic gates connected by electronic fuses. These fuses can be ‘blown’ (by programming) to obtain different circuit configurations. Semi-customized chips that give high packing density at reasonable cost. Three classes of PLDs are : Programmable Logic Array (PLA) Programmable Read Only Memory (PROM) Programmable Array Logic (PAL) CS Programmable Logic Devices

5
**Programmable Logic Devices**

Fixed AND array Fused programmable OR array Fuses Inputs Outputs Programmable Read Only Memory (PROM) Fixed OR array Fused programmable AND array Fuses Inputs Outputs Programmable Array Logic (PAL) Inputs Fused programmable OR array Fuses Outputs AND array Programmable Logic Array (PLA) CS Programmable Logic Devices

6
**Programmable Logic Devices**

“Programming” an array – blowing the fuses. A A' B B' x1 x2 x3 A A' B B' x1 = A.B x2 = A'.B x3 = A.B' (a) Unprogrammed (b) Programmed Example of a basic AND array CS Programmable Logic Devices

7
**Programmable Logic Devices**

PLDs use diodes. A PN diode is an electronic device formed by creating a junction of two types of semi-conductor materials, p type and n type. Forward-biased: When p side (anode) is more positive than n side (cathode), it behaves as a closed switch. Reverse-biased: When cathode is more positive than anode, it behaves as an open circuit. P N + - Anode Cathode Forward-biased (closed circuit) + - PN junction diode and schematic symbol. Reverse-biased (open circuit) CS Programmable Logic Devices

8
**PN Diode Operation PN diode operation for digital applications. (a)**

B +V A B (a) (d) (b) +V (e) A=0 B=0 A=1 B=1 A=0 B=0 +V A=1 B=1 (c) (f) PN diode operation for digital applications. (a) With pull-up resistor. (b) Reverse-biased: diode open; B pulled up to 1. (c) Forward-biased: diode shorted, forcing B to 0. (d) With pull-down resistor. (e) Reverse-biased: diode open; B pulled down to 0. (f) Forward-biased: diode shorted, forcing B to 1. CS PN Diode Operation

9
**AND Logic Arrays AND function realised with a diode array. (a) (c) (d)**

f(A,B,C) = 0 +V B=1 C=1 A f(A,B,C) = A.B.C +V B C (a) (c) (d) A=0 f(A,B,C) = 0 +V B=0 C=1 (b) A=1 f(A,B,C) = 1 +V B=1 C=1 AND function realised with a diode array. (a) Basic configuration. (b) All diodes open; f pulled up to 1. (c) One diode shorted, forcing f to 0. (d) Multiple diodes shorted, forcing f to 0. CS AND Logic Arrays

10
**OR Logic Arrays OR function realised with a diode array. (a) (b) (c)**

f(A,B,C) = A+B+C B C (b) A=0 f(A,B,C) = 0 B=0 C=0 (c) A=1 f(A,B,C) = 1 B=0 C=0 OR function realised with a diode array. (a) Basic configuration. (b) All diodes open; f pulled up to 0. (c) One diode shorted, forcing f to 1. CS OR Logic Arrays

11
**Two-level AND-OR Arrays**

AND and OR circuits can be interconnected to realise any arbitrary switching function. Example: f(a,b,c)=a.b.c'+b'.c CS Two-level AND-OR Arrays

12
**Programmable Logic Array (PLA)**

Combination of a programmable AND array followed by a programmable OR array. Example: Design a PLA to realise the following three logic functions and show the internal connections. f1(A,B,C,D,E) = A'.B'.D' + B'.C.D' + A'.B.C.D.E' f2(A,B,C,D,E) = A'.B.E + B'.C.D'.E f3(A,B,C,D,E) = A'.B'.D' + B'.C'.D'.E + A'.B.C.D CS Programmable Logic Array (PLA)

13
**Realising Logic Functions with PLAs**

f1(A,B,C,D,E) = A'.B'.D' + B'.C.D' + A'.B.C.D.E' f2(A,B,C,D,E) = A'.B.E + B'.C.D'.E f3(A,B,C,D,E) = A'.B'.D' + B'.C'.D'.E + A'.B.C.D A B C D E P1 P3 P4 P6 P5 P2 P7 Programmable OR array Programmable AND array A'B'D' X B'CD' A'BCDE' A'BE B'CD'E B'C'D'E A'BCD f1 f2 f3 A'.B'.D' B'.C.D' A'.B.C.D.E' CS Realising Logic Functions with PLAs

14
**Read-Only Memory (ROM)**

A semi-conductor memory is a device where data can be stored and retrieved. Logically, this memory device can be regarded as a table of memory cells (data). 1 2 3 : n Addresses 1-word data 1-bit data word size CS Read-Only Memory (ROM)

15
**Read-Only Memory (ROM)**

A Read-Only Memory (ROM) is a memory device where data are read from, but not written to. Writing is done at time of customisation, or, by special programming devices (programmable ROM). Any Boolean expression can be implemented using ROM. Procedure: Obtain a truth table, treat the inputs as addresses and outputs as data. Advantage: Boolean functions directly implemented. Disadvantages: Don’t care conditions not used, and limited input variables (e.g. 10 inputs – 1K, 16 inputs – 64K, 20 inputs – 1M). CS Read-Only Memory (ROM)

16
**Read-Only Memory (ROM)**

Different types of ROM devices available: ROM: Read-Only Memory Data written into memory by mask programming during manufacturing time. Expensive start-up cost but economical for high volume. Cannot be erased after data are programmed in. PROM: Programmable ROM Semi-custom chip. Fuses can be broken by special hardware programmer unit. Cost-effective for low volumes. Cannot be erased after programming. CS Read-Only Memory (ROM)

17
**Read-Only Memory (ROM)**

EPROM: Erasable PROM Similar to PROM except that data can be completely erased by exposure to ultra-violet light. EEPROM: Electrically Erasable PROM A PROM where data can be selectively erased by hardware programmer unit, rather than by ultra-violet light. Useful for remote devices which can be re-programmed from a distance. CS Read-Only Memory (ROM)

18
**Programmable Read-Only Memory (PROM)**

Devices with fixed AND array (which is a decoder) and programmable OR array. The AND array (decoder) generates all 2n possible minterm products of its n inputs (often referred to as n-to-2n decoder). n input lines, m output lines. Bit combination of input variables – address. Bit combination of output lines – word (each word contains m bits). CS Programmable Read-Only Memory (PROM)

19
**Programmable Read-Only Memory (PROM)**

I0 I1 I2 m0 m2 m3 m5 m4 m1 m7 Programmable OR array Fixed AND array X O1 O2 Ok m6 . Minterms Programmable read-only memory (PROM) can realize K functions f(I2,I1,I0). CS Programmable Read-Only Memory (PROM)

20
**Programmable Read-Only Memory (PROM)**

2n x m ROM n inputs m outputs 2n x m ROM => 2n words, each word m bits => 2n x m bits CS Programmable Read-Only Memory (PROM)

21
**Programmable Read-Only Memory (PROM)**

5 x 32 decoder A0 A1 A2 A3 A4 1 2 31 F1 ... . F2 F3 F4 Minterms Address input 128 fuses Logic construction of a 32 x 4 ROM. CS Programmable Read-Only Memory (PROM)

22
**Realising Logic Functions with PROMs**

Example (8 x 3 ROM): f1(A,B,C) = A.B + B'.C f2(A,B,C) = (A+B'+C).(A'+B) f3(A,B,C) = A + B.C First, we convert each function to canonical SOP form. f1(A,B,C) = A.B + B'.C = A.B.C' + A.B.C + A'.B'.C + A.B'.C = S m(1,5,6,7) = (A+B'+B).(A'+B+C').(A'+B+C) = P M(2,4,5) = S m(0,1,3,6,7) f3(A,B,C) = A + B.C = A.B'.C' + A.B'.C + A.B.C' + A.B.C + A'.B.C = S m(3,4,5,6,7) CS Realising Logic Functions with PROMs

23
**Realising Logic Functions with PROMs**

B A m0 m2 m3 m5 m4 m1 m7 Programmable OR array Fixed AND array X f1 = S m(1,5,6,7) f2 = S m(0,1,3,6,7) f3 = S m(3,4,5,6,7) m6 Minterms CS Realising Logic Functions with PROMs

24
**Realising Logic Functions with PROMs**

3 x 8 decoder C B A 1 2 3 4 5 6 7 f1 = Sm(1,5,6,7) Minterms Address input f2 = Sm(0,1,3,6,7) f3 = Sm(3,4,5,6,7) 8 x 3 ROM 0: 1: 2: 3: 4: 5: 6: 7: CS Realising Logic Functions with PROMs

25
**Programmable Array Logic (PAL)**

Introduced in late 1970s by Monolithic Memories Inc. as lower cost replacement for logic gates, PROMs, and PLAs. PAL has programmable AND array and fixed OR array. Less general than PLA but easier to manufacture and design. Product terms belong to different OR gates, cannot be shared. CS Programmable Array Logic (PAL)

26
**Programmable Array Logic (PAL)**

D P1 P2 P3 O1 P4 P5 P6 O2 Programmable AND array Fixed OR array CS Programmable Array Logic (PAL)

27
**Realising Logic Functions with PALs**

Procedure is to obtain minimal SOP expressions. Example: fa(A,B,C,D) = A'.B'.D' + B'.C.D' + A'.B.C.D fb(A,B,C,D) = A'.B + B'.C.D' fc(A,B,C,D) = A'.B'.D' + B'.C'.D' + A'.B.C.D CS Realising Logic Functions with PALs

28
**Realising Logic Functions with PALs**

fa(A,B,C,D) = A'.B'.D' + B'.C.D' + A'.B.C.D fb(A,B,C,D) = A'.B + B'.C.D' fc(A,B,C,D) = A'.B'.D' + B'.C'.D' PAL realisation of fa, fß and fr. A P1 P2 P3 fa P4 P5 P6 fb fc B C D x CS Realising Logic Functions with PALs

29
End of segment

Similar presentations

Presentation is loading. Please wait....

OK

Karnaugh Map Adjacent Squares

Karnaugh Map Adjacent Squares

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on two point perspective examples Ppt on intel core i3 processor Ppt on hotel industry in india 2013 Ppt on hydrostatic forces on submerged surfaces Ppt on circuit breaker testing Ppt on measuring area and volume 3rd grade Ppt on agriculture in india pdf Ppt on travelling salesman problem using genetic algorithm Ppt on swami vivekananda books Ppt on evolution and classification of computers