Semi-Detailed Bus Routing with Variation Reduction Fan Mo, Synplicity Robert Brayton, UC Berkeley Presented by: Philip Chong, Cadence.

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Semi-Detailed Bus Routing with Variation Reduction Fan Mo, Synplicity Robert Brayton, UC Berkeley Presented by: Philip Chong, Cadence

Outline Why bus routing. The orientation determination problem. Bus routing flow overview. The algorithm. Experimental results. Future work.

Why Bus Routing Bit-wise wire length/delay matching. Save runtime. –Routing a representative bit (what we call virtual net). Usually better routability –Less twisting and entangling. Better variation immunity. –All bits receive similar variations.

Existing Bus Routers Route a representative bit rather than all bits. –Persky and Tran, DAC 84 Fanout-1 bus –Rafiq et al, ISPD 02 0-bend, 1-bend, 2-bend bus topologies. –Xiang et al, DAC 03 –Law and Young, ISPD 05 –Chen and Chang, ISPD 05

The Turning Points! The arrangement of the turning points is the key to successful bus routing.

The Node Orientation The virtual net –An abstract view of the bus. –Bused pins become pin nodes. –All other points become non-pin nodes. The arrangement of the bits at a node is called the orientation. –The direction from LSB towards MSB.

Orientation and Orientation Set A pin node has a fixed orientation. –Always 0 o or 90 o (N, W, S or E) A non-pin node may have several possible orientations. –Always 45 o (NE, NW, SE, SW) All possible orientations of a node form an orientation set. pin nodes Or.Set (single orientation) non-pin nodes Or.Set NWNESWSENHEVSHWV TPTNAL

Orientation and Orientation Set Adjacent nodes must have compatible orientation sets. empty orientation set

Orientation and Orientation Set Special case: Interlocking. –When two non-pin nodes are connected by a short segment, the connection must be a Z-shape. –The orientation sets of the two nodes are interlocked. What is short? Distance less than the all-bit routing width of the bus.

Bus Routing Flow

The Algorithm

Step 1: Preparation

The Algorithm Step 2: Virtual net routing

The Algorithm Step 3: Orientation set generation

The Algorithm Step 4: Fix –Add extra blockage to avoid using certain segments. –Re-route (Step 2). –Redo orientation set generation (Step 3). –Try a few times. If still fails, abort.

The Algorithm Step 5: Orientation determination and deviation reduction –A forward propagation from the driver pin node can determine the orientation for each node (from its orientation set). –Flexibility may exist, if for certain nodes, more than one orientation are valid choices. –Such flexibility allows minimization of bit- wise driver-load wire length/delay deviation. Bit-wise wire length deviation = the (absolute) difference between MSB driver-load length and LSB driver-load length.

The Algorithm Step 5: Orientation determination and deviation reduction –No minimization: One round of forward propagation determines the orientations for all nodes. Complexity O(U), where U is number of nodes. orientation setsno minimization

The Algorithm Step 5: Orientation determination and deviation reduction –Minimizing total/maximum deviation: Implicitly enumerate possible combinations and pick the best one. Complexity O(F×U), where F is fanout. minimizing max deviationminimizing total deviation

The Algorithm methodtotal deviation max deviation no minimization11Δ3Δ3Δ minimizing total deviation5Δ5Δ3Δ3Δ minimizing max deviation7Δ7Δ2Δ2Δ Step 5: Orientation determination and deviation reduction

Experimental Results 1 1024 unit-tests (single bus routing) –Bit-width=8,16,32,64. –Fanout=1~16. –0~2 random routing blockages. Our bus router (this) is compared with a bus-aware reference router (rrouter).

Experimental Results 1 Success rate. both routers succeed this succeed only rrouter succeed only both fail

Experimental Results 1 this vs rrouter Run time: 20X faster. Wire length: Better when fanout<11; 2% longer when fanout approaches 16. Ave. driver-load wire length deviation: 188% less. Max. driver-load wire length deviation: 469% less. Ave. driver-load delay deviation: 286% less. Max. driver-load delay deviation: 273% less.

Experimental Results 1 Under variation. rrouter has max bit-wise delay deviation of 25ps, while this has only 7ps.

Experimental Results 2 Comparison of two flows -the reference router (rrouter) -our router routes bus, forward annotate and then the reference router finishes the rest (this+rr) total wire length ( m) #viaruntime (min:sec) designrrouterthis+rrrrouterthis+rrrrouterthis+rr A1425823421889425736213:253:27 A2779634781627721360925:114:45 A310135621000581860566691:251:10 A474728887453371689449273:593:54 A55770986575563927482224713:574:08 Total wire length and via number 5 real designs. 0.5% shorter25% less7.5% faster

Experimental Results 2 average deviationmaximum deviationmax dev w/ variation designrrouterthis+rrrrouterthis+rrrrouterthis+rr A124.16.5764.119.368.019.3 A242.58.3411318.912119.7 A333.29.4979.522.084.128.4 A454.17.9526521.154270.6 A545.99.1616222.826640.9 Average/max driver-load delay deviations (ps) (buses only) 3X smaller6X smaller

Experimental Results 2 Final routing of design A4 by rrouter

Experimental Results 2 Final routing of design A4 by this+rr

Future Work Embed the algorithm in floorplanning, global routing … Bus validity checking for designers manually floorplanning modules.

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