# ELEN 468 Lecture 261 ELEN 468 Advanced Logic Design Lecture 26 Interconnect Timing Optimization.

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ELEN 468 Lecture 261 ELEN 468 Advanced Logic Design Lecture 26 Interconnect Timing Optimization

ELEN 468 Lecture 262 Buffers Reduce Wire Delay t_unbuf = R( cx + C ) + rx( cx/2 + C ) t_buf = 2R( cx/2 + C ) + rx( cx/4 + C ) + t b t_buf – t_unbuf = RC + t b – rcx 2 /4 R cx/4 rx/2 cx/4 rx/2 C C R x ∆t x/2

ELEN 468 Lecture 263 Buffers Improve Slack RAT = 300 Delay = 350 Slack = -50 RAT = 700 Delay = 600 Slack = 100 slack min = -50 RAT = 300 Delay = 250 Slack = 50 RAT = 700 Delay = 400 Slack = 300 slack min = 50 Decouple capacitive load from critical path RAT = Required Arrival Time Slack = RAT - Delay

ELEN 468 Lecture 264 Problem Formulation Given A routing tree RAT at each sink A buffer type RC parameters Candidate buffer locations Find buffer insertion solution such that the slack min is maximized

ELEN 468 Lecture 265 Candidate Buffering Solutions

ELEN 468 Lecture 266 Candidate Solution Characteristics Each candidate solution is associated with v i : a node c i : downstream capacitance q i : RAT v i is a sink c i is sink capacitance v is an internal node

ELEN 468 Lecture 267 Van Ginneken’s Algorithm Start from sinks Candidate solutions are generated Candidate solutions are propagated toward the source

ELEN 468 Lecture 268 Solution Propagation: Add Wire c 2 = c 1 + cx q 2 = q 1 – rcx 2 /2 – rxc 1 r: wire resistance per unit length c: wire capacitance per unit length (v 1, c 1, q 1 ) (v 2, c 2, q 2 ) x

ELEN 468 Lecture 269 Solution Propagation: Insert Buffer c 1b = C b q 1b = q 1 – R b c 1 – t b C b : buffer input capacitance R b : buffer output resistance t b : buffer intrinsic delay (v 1, c 1, q 1 ) (v 1, c 1b, q 1b )

ELEN 468 Lecture 2610 Solution Propagation: Merge c merge = c l + c r q merge = min(q l, q r ) (v, c l, q l )(v, c r, q r )

ELEN 468 Lecture 2611 Solution Propagation: Add Driver q 0d = q 0 – R d c 0 = slack min R d : driver resistance Pick solution with max slack min (v 0, c 0, q 0 ) (v 0, c 0d, q 0d )

ELEN 468 Lecture 2612 Example of Solution Propagation (v 1, 1, 20) 22 r = 1, c = 1 R b = 1, C b = 1, t b = 1 R d = 1 v1v1 (v 3, 5, 8) Add wire v1v1 (v 2, 3, 16) Add wire v1v1 (v 2, 1, 12) Insert buffer v1v1 (v 3, 3, 8) Add wire slack = 3 Add driver slack = 5Add driver

ELEN 468 Lecture 2613 Example of Merging Left candidates Right candidates Merged candidates

ELEN 468 Lecture 2614 Solution Pruning Two candidate solutions (v, c 1, q 1 ) (v, c 2, q 2 ) Solution 1 is inferior if c 1 > c 2 : larger load and q 1 < q 2 : tighter timing

ELEN 468 Lecture 2615 Pruning When Insert Buffer They have the same load cap C b, only the one with max q is kept

ELEN 468 Lecture 2616 Wire Segmenting Faster runtime Better solution quality

ELEN 468 Lecture 2617 Multiple Buffer Types (v 1, 1, 20) 22 r = 1, c = 1 R b = 1, C b = 1, t b = 1 R b2 = 0.5, C b2 = 2, t b2 = 0.5 R d = 1 v1v1 (v 2, 3, 16) v1v1 (v 2, 1, 12) v1v1 (v 2, 2, 14)

ELEN 468 Lecture 2618 Using Inverters Less cost

ELEN 468 Lecture 2619 Handle Polarity - Negative Positive - - - - - -

ELEN 468 Lecture 2620 Slew Constraints When a buffer is inserted, assume ideal slew rate at its input Check slew rate at downstream buffers/sinks If slew is too large, candidate is discarded

ELEN 468 Lecture 2621 Capacitance Constraints Each gate g drives at most C(g) capacitance When inserting buffer g, check downstream capacitance. If > C(g), throw out candidate Total cap = 500 ff

ELEN 468 Lecture 2622 Consider Cost/Power A solution is also characterized by cost w A solution is inferior if it is poor on all of c, q and w At source, a set of solutions with tradeoff of q and w w can be total capacitance or the number of buffers

ELEN 468 Lecture 2623 Cost-Slack Trade-off

ELEN 468 Lecture 2624 Continuous Wire Sizing Min delay wire shape: w(x) = a(e -bx ) x

ELEN 468 Lecture 2625 Two Types of Wire Sizing Uniform Wire Sizing (UWS) Wire Tapering (TWS)

ELEN 468 Lecture 2626 TWS versus UWS TWS UWS

ELEN 468 Lecture 2627 Why Uniform Wire Sizing? Empirically, UWS almost as good as TWS Tapering info hard to give to router Better congestion and space management Extraction, detailed routing, verification? Can do it simultaneously with buffering

ELEN 468 Lecture 2628 Wire Sizing to Minimize Weighted Delay Sum Minimize  i t i  i weight, t i Elmore delay to sink i Properties Separability Monotone property Dominance property

ELEN 468 Lecture 2629 Wire Sizing: Separability For given wire sizing along a path, optimal wire sizing for each subtree off the path can be carried out independently

ELEN 468 Lecture 2630 Wire Sizing: Monotone Property Ancestor edges cannot be narrower than downstream edges

ELEN 468 Lecture 2631 Wire Sizing: Dominance Property For each edge, if its width in solution W  its width in solution W’, then W dominates W’ Local refinement: size each edge independently to minimize delay sum while other edges are fixed Assume W* is the optimal solution If W dominates W*, then W still dominates W* after local refinement If W is dominated by W*, then W is still dominated by W* after local refinement

ELEN 468 Lecture 2632 Optimal Wire Sizing Maximum width solution Each edge starts with max width Perform local refinement Minimum width solution Each edge starts with min width Perform local refinement Enumerate possibilities between min and max width solutions

ELEN 468 Lecture 2633 Wire Sizing to Maximize the Min Slack Separability is not true here Can be solved with dynamic programming Can be integrated with buffer insertion

ELEN 468 Lecture 2634 Simultaneous Buffer Insertion and Wire Sizing