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Ispd-2007 Repeater Insertion for Concurrent Setup and Hold Time Violations with Power-Delay Trade-Off Salim Chowdhury John Lillis Sun Microsystems University of Illinois at Chicago Sun Microsystems University of Illinois at Chicago

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Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations, and future directions Acknowledgements

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Motivation Traditional Flow Max Mode Optimization Logic Drops More Max Mode Optimization Close To Tape Out: Min Mode Analysis and Fixes Challenges: Resizing bits in banks? Repeater reposition? Room for more repeaters? Don’t aggravate critical paths!

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Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations, and future directions Acknowledgements

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Basic Algorithm in the Late Mode Try repeater sizes to generate solutions: (c, q) pairs Identify and prune sub-optimal; Merging @ fanout: avoid sub-optimal combinations Select the solution with highest q @ driver

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Concurrent Min-Max Model q b close to q bd is better higher c helps to achieve q b closer to q bd (Note: initially q b q bd ) if (c b1 (c b1, q b1 ) Objective Function: Late-Mode q w Constraint: Early-Mode Arrival Time at the Driver: q bd s 2 is sub-optimal compared to s 1 if (s 1 => s 2 ) s 2 is sub-optimal in late mode and s 2 is sub-optimal in early mode Solution: (c w, q w, c b, q b ) Late mode: s 1 => s 2 if (c w2 < c w1 ) and (q w2 < q w1 )

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Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations and future directions Acknowledgements

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Pruning a List of Solutions Four rules: c w2 c w1 in all cases: Case I: q b1 > q bd and q b2 q bd : Case II: q b1 > q bd and q b2 > q bd : Case III: q b1 q bd and q b2 q bd : Case IV: q b1 q bd and q b2 > q bd : s 2 cannot be pruned Prune s 1 if (c w1 = c w2 ) and (q w1 q w2 ) Prune s 2 if (q w2 q w1 ), (c b2 c b1 ) and (q b2 q b1 ) Prune s 1 if (q w1 q w2 ), (c w1 = c w2 ), (c b1 c b2 ), (q b1 q b2 ) Prune s 2 if (q w2 q w1 ) Prune s 1 if (c w1 = c w2 ), and (q w1 q w2 ) Prune s 2 if (q w2 q w1 )

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Identifying sub-optimal solutions Solution c w q w 1 10100 2 11102 3 13101 4 15106 5 15105 6 16104 7 17103 8 18103 919109 10 20110 11 21108 12 22109 13 22111 14 23109 1524110 c b q b 550 651 652 752 854 955 655 854 1056 1157 1258 1359 1460 957 1156 Dominating Sol. 2 5 9

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Complexity Reduction in Pruning sGPairSOAction 1ØNoneInsert 2{1}(1,2)Insert 3{1,2}(2,3)3Delete 4{1,2}NoneInsert 5{1,2,4}(4,5)Insert 6{1,2,5,4}(5,6) (4,6)Insert 7{1,2,6,5,4}(6,7)7Delete 8{1,2,6,5,4}(6,8) (5,8)8Delete

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Further Reduction in Comparison Set Set G can be stored in a 2-Way binary tree: 1 st branch: q w 2 nd branch: q b 14G={1,2,6,5,4,11,9,12,10,13}(9,14)14Delete How to quickly identify the dominating solution 9 in group G?

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Example Binary Tree Solution14: c w =23q w =109c b =9q b =57 Dominating Solution: 9: c w =19q w =109c b =10q b =56 G = {1,2,6,5,4,11,9,12,10,13} {1,2,6,5,4,11}{9,12,10,13} qwqw {9}{12,10,13} qbqb

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Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations and future directions Acknowledgements

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Merging Multiple Branches

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Late Mode Merging LS = {(1,1)->(1X{2:3}), (2,2)->(2,3)}

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Early Mode Merging ES = {(2,2)->(2X{1,3}), (1,2)->(1X{1,3})}

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Identifying Non-Suboptimal Combinations LS = {(1,1)->(1X{2:3}), (2,2)->(2,3)} ES = {(2,2)->(2X{1,3}), (1,2)->(1X{1,3})} Sub-Optimal combinations are: (2,3) Non-suboptimal combinations: (1,2), (1,3), (2,1), and (1,1) Looking for a more efficient technique __________ _____

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Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations and future directions Acknowledgements

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Delay-Power Trade-Off How to avoid the flat region?

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Techniques for Trade-Off John Lillis (ICCAD-95 ) Prune a solution if inferior in both p and q Algorithm highlights: Put solutions into power bins Intra-bin Pruning: Linear Inter-bin Pruning: more than linear Merging: all bin-pairs All trade-offs are explicitly computed and retained Final selections at the driver Issues: Large # of bins (esp. if slew dependent) Number of bin-pairs can be O(n 2 ) Large solution space => run time

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Implicit Power-Delay Trade-Off Desired trade-off is captured in a parameter: = delay/ power For example, if 0.01 ps delay reduction for a power dissipation of 1 w is acceptable, then = 0.01 ps/ w q a = q - *P (P = power/area); *P is a “penalty” Features:Trade-Off is Implicit Controlled Solution Space and Run Time Pruning a list: if (c 2 c 1 ) and (q 2a (c 2, q 2a ): Facilitates min-power solution (test nets) Merging Much detailed: could not include in this paper

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Too Little to Gain @ Too Much Price Penalty#net buffered#repeaters 0.023045126 0.519282628

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Outline Motivation Modelling late & early modes concurrently Identifying sub-optimal solutions in a list The merging problem Power-Delay Trade-Off Interaction between late & early modes (examples) Conclusions, limitations and future directions Acknowledgements

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Interaction Betwn. Late & Early Modes Caseq b1 (ps)q b2 (ps)Repeaters at Locations I1077132x at 3 and 7 II1287132x at 2 and 8; b mt at 5 III1288932x at 2, 16x at 8 and b mt at 5 IV12810132x at 2, 16x at 6 and 8, b mt at 5

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Conclusion & Future Directions A new model for repeater insertion problem Early-mode timing requirement is a constraint Helps avoid aggressive late-mode optimization creating new early mode violations Should speed up design turn-around time by avoiding ECO’s to satisfy early-mode violations Techniques for satisfying maximum and minimum slew values, accurate timing to consider these slew values and avoid the flat region in the power-delay curve

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Limitations & Future Directions Limitations Run time complexity Slack Budgeting Future research topics include: Combine gate sizing and repeater insertion Cone based Graph based Better merging techniques Controlling variations: process, voltage and temperature Hierarchical We welcome collaboration with academia

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Acknowledgements Reviewers for detailed feedback Rob Mains for review & encouragements Aman Joshi and Sun Management for support Program Committee and the Organizers

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Thank You

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Satisfying Min-Max Slews

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