Download presentation

Presentation is loading. Please wait.

Published byBrendon Sprott Modified over 3 years ago

1
THERMAL-AWARE BUS-DRIVEN FLOORPLANNING PO-HSUN WU & TSUNG-YI HO Department of Computer Science and Information Engineering, National Cheng Kung University 1

2
OUTLINE INTRODUCTION PROBLEM FORMULATION ALGORITHM EXPERIMENTAL RESULTS CONCLUSION 2

3
INTRODUCTION Higher operating frequencies may cause increased power density. More power density means that more heat is produced, then the enormous heat dissipation causes high temperature on the chip. High temperature greatly aggravates electro-migration (EM) in the metal wire and reduces their mean-time-to-failure (MTTF). At worst, it can lead to the eventual loss of one or more connections and permanent chip failure. 3

4
INTRODUCTION The bus which is a collection of wires is widely used for transferring data and control signals between different modules in multicore SoC designs. Thus, the bus consumes much energy and dissipates great amount of heat. To minimize the chip temperature, it avoids routing the bus through those hotspots. 4

5
INTRODUCTION 5

6
PROBLEM FORMULATION In the thermal-aware bus-driven floorplanning problem, the following information is given: 1)A set of n modules M = {m 1, m 2,...,m n }. Each module mi is associated with height h i, width w i, and power density P, where h i, w i, P R+. 2)A set of m buses B = {b 1, b 2,..., b m }. Each bus b j has a width bw j and goes through a set of modules, where bw j R +. 6

7
PROBLEM FORMULATION The task is to determine the module position and the bus routing path, and the objective is to optimize the chip area, total bus wirelength, and the chip temperature under the following constraints: 1)No overlap between various horizontal and vertical components of the bus. 2)No overlap is allowed between different modules. 3)No extra via is allowed at the bend of the diagonal bus. 7

8
ALGORITHM At the beginning of the algorithm, an initial floorplan represented by SP [16] is derived, and then HotSpot [17] is used to generate the thermal profile of each module which is stored in a one-dimensional array for further reference. In each SA iteration, it adopts the superposition of thermal profiles to estimate the module temperature. Then the temperature of all bus routing paths are derived, bus routing topologies are constructed away from hotspots. 8

9
ALGORITHM After that, several horizontal and vertical buses are obtained, then it derives the bus ordering between different buses and determines the coordinate of each bus based on the bus ordering [5]. Since no extra via is allowed at the bend of the diagonal bus, a modified graph coloring algorithm is adopted to assign each bus to the different layers [12]. After finishing the bus routing, it uses the bus thermal model to update the module temperature. 9

10
ALGORITHM SP is used to represent the floorplan, and three operations are used to perturb the current floorplan in each SA iteration: (1) Rotate. (2) Swap. (3) Reverse. The cost function is defined as follows: Cost = α A + β W + γ T where A is the chip area, W is the bus wirelength, T is the peak module temperature on the floorplan, and α, β, and γ are user-defined parameters. 10

11
ALGORITHM After the SA stage, a post-processing is performed to obtain a better chip area by changing either the width or height of some modules that are on the critical path [5]. After the soft module adjustment, HotSpot is used for performing the thermal simulation to obtain accurate module temperature, then the bus thermal model is applied to update the module temperature. 11

12
ALGORITHM A.Thermal Profile Generation It first generates the thermal profile of each module in advance and divides the thermal profile of each module into m×n grids, then all grids can be stored in a one-dimensional array for further reference. In this paper, the thermal profile of each module is divided into 4×4 grids to get a quick evaluation of the module temperature, and the floorplans in experimental results are divided into 64×64 grids to obtain a accurate simulation. 12

13
ALGORITHM B. Bus Thermal Model The heat flow equation for a one-dimensional bus is defined as follows [22], [23]: 13 where T line Bus temperature kmkm *1 Thermal conductivity k ins *2 Thermal conductivity ρMetal electrical resistivity T ref Underlying substrate temperature tmtm *1 Thicknesst ins *2 ThicknessβTemperature coefficient of the resistance w *1 WidthI rms Root-mean-square current *1 of the one-dimensional bus *2 of the insulator

14
ALGORITHM B. Bus Thermal Model the constant current density is used to compute the temperature of the bus; thus, equations (5) and (6) are transformed into equations (7) and (8): 14 D is the constant current density in a one-dimensional bus. To reduce the computation complexity, equation (4) is further transferred to equation (9) T ref (x) is a constant value (T constant ) for a short bus length, and T R = T ref (x).

15
ALGORITHM B. Bus Thermal Model After the process of the HotSpot simulation, the floorplan is partitioned into m×n grids and the temperature of each grid is computed. For each grid that is overlapped by a bus, equation (9) is computed to update the temperature of the selected grid. At the end of each iteration of SA process, equation (9) is computed to update the temperature of those modules which are overlapped by a bus. 15

16
ALGORITHM C. Routing Topology Construction To obtain more possible bus topologies, the nearest neighbor in four directions of each bus module is first explored to obtain a set of routing paths which include horizontal, vertical, or diagonal connections. the routing topology with the lowest temperature is chosen to route away from hotspots. To make a balance between wirelength and temperature, the diagonal connection that is not considered for a pair of modules has a horizontal or vertical connection during finding the nearest neighbor. 16

17
ALGORITHM C. Routing Topology Construction The temperature of each routing path is derived by averaging the temperature of those modules that are overlapped with the routing path. After that, all routing paths are sorted according to the temperature in non-decreasing order. Finally, routing topologies are constructed from choosing the path with the lowest temperature to keep the bus away from hotspots. 17

18
ALGORITHM D. Perturbation Since the thermal profile of the rotated module will be changed, an update of the thermal profile is required for the rotated module after the operation. The swap operation is modified to separate hotspots on the floorplan and the reverse operation is the same as the usual operation in SP. All three operations change the distribution of thermal gradient on the floorplan which further modifies the module temperature. Therefore, the module temperature must be recalculated by superposition operation after each perturbation. 18

19
ALGORITHM D. Perturbation 19 1) Rotate

20
ALGORITHM D. Perturbation The height of module M 1 is x and the width of module M 1 is a × x, where a is the aspect ratio of the module M 1. It assumes that the allowable variation in area is ±b% compared to the area of the target module. The upper bound and lower bound of the candidate height are z and y, respectively. The upper bound and lower bound of the candidate width are a × z and a × y, respectively. 20 2) Swap

21
EXPERIMENTAL RESULTS 21

22
EXPERIMENTAL RESULTS 22

23
CONCLUSION This work propose a bus-driven floorplanning algorithm that considers the practical impact of the thermal effect. Experimental results demonstrated that the proposed floorplanner can effectively separate hotspots and reduce the chip temperature. 23

Similar presentations

OK

Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.

Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google