Presentation is loading. Please wait.

Presentation is loading. Please wait.

ISPD 2000, San DiegoApr 10, 2000 --1-- Requirements for Models of Achievable Routing Andrew B. Kahng, UCLA Stefanus Mantik, UCLA Dirk Stroobandt, Ghent.

Published by Modified over 8 years ago

Similar presentations

Presentation on theme: "ISPD 2000, San DiegoApr 10, 2000 --1-- Requirements for Models of Achievable Routing Andrew B. Kahng, UCLA Stefanus Mantik, UCLA Dirk Stroobandt, Ghent."— Presentation transcript:

1 ISPD 2000, San DiegoApr 10, 2000 --1-- Requirements for Models of Achievable Routing Andrew B. Kahng, UCLA Stefanus Mantik, UCLA Dirk Stroobandt, Ghent Univ. Supported by Cadence Design Systems, Inc. and the MARCO Gigascale Silicon Research Center

2 ISPD 2000, San DiegoApr 10, 2000 --2-- Outline Models of achievable routing Review of existing models Validation of models through experiments! Experimental analysis of assumptions Future model requirements Conclusions

3 ISPD 2000, San DiegoApr 10, 2000 --3-- –wirelength estimation models (Donath, …) –actual placement information Models of achievable routing Required versus available resources

4 ISPD 2000, San DiegoApr 10, 2000 --4-- Models of achievable routing Required versus available resources limited by routing efficiency factor  r

5 ISPD 2000, San DiegoApr 10, 2000 --5-- Models of achievable routing Required versus available resources limited by power/ground (signal net fraction s i )

6 ISPD 2000, San DiegoApr 10, 2000 --6-- Models of achievable routing Required versus available resources limited by via impact factor v i (ripple effect) utilization factor U i (available / supplied area)

7 ISPD 2000, San DiegoApr 10, 2000 --7-- Use of achievable routing models Optimizing interconnect process parameters for future designs (number of layers, wire width and pitch per layer,...) With given layer characteristics: predict the number of layers needed If number of layers fixed: oracle “(not) routable!” (SUSPENS, GENESYS, RIPE, BACPAC, GTX) Supplying objectives that guide layout tools to promising solutions (wire planning)

8 ISPD 2000, San DiegoApr 10, 2000 --8-- Validation is key Models must be accurate, must support empirical verification and calibration No existing model is validated with real place-and-route data Our work concentrates on validation: –understanding reasons for validation gap –processes for model validation –improvements needed in future models

9 ISPD 2000, San DiegoApr 10, 2000 --9-- Review of existing models Sai-Halasz [Proc. IEEE, 1995] –power/ground: s i 20% –routing efficiency:  r = 40% –via impact: each layer blocks 15% on layers below with same pitch –model is widely used –model is rather pessimistic

10 ISPD 2000, San DiegoApr 10, 2000 --10-- Review of existing models (cont.) Chong and Brayton [SLIP, 1999] –layer assignment model layer pairs form tiers (H and V) wires are routed on 1 tier shorter wires on lower tiers –available resources model constant routing efficiency for all layers:  r = 65% via impact factor v i based on actual via area –each wire uses 2 via stacks (block wires on lower layers) –total number of wires per layer (thus vias) defined by layer assignment model H H V V } } tier

11 ISPD 2000, San DiegoApr 10, 2000 --11-- Review of existing models (cont.) Chen et al. [private communication, 1999] –layer assignment model similar to Chong’s –available resources model constant routing efficiency (40% <  r < 66%) via impact model –terminal vias and turn vias –each wire uses 2 via stacks –number of terminal vias defined by layer assignment model –sparse via model = Chong –dense via model: give up 1 track every X tracks –results in via impact proportional to sqrt(Chong’s impact factor) H H V V } } tier tracks

12 ISPD 2000, San DiegoApr 10, 2000 --12-- Model validation Models can be validated only by testing against comparable experimental results –none of reviewed models was validated –even simple comparison: huge differences 70 65 60 55 50 45 40 35 01345 Via fill rate (%) Utilization factor/layer (%) Sai-Halasz (M4) Sai-Halasz (M1) Chong Chen Sai-Halasz (M3) Sai-Halasz (M2)

13 ISPD 2000, San DiegoApr 10, 2000 --13-- Model validation (cont.) Experimental validation –Typical industry standard-cell block design 42.000 cells, 1999, 5 layers Cadence placement and gridded routing tools same pitch (1  m) for all layers via size.62  m all pins for cells are on M1 Experimental validation –ensure congested design Via fill rate (%) Utilization factor (%) Sai-Halasz (M4) Sai-Halasz (M1) Chong Chen Sai-Halasz (M3) Sai-Halasz (M2) 75 65 60 55 50 45 40 35 30 70 Exp M2 0123465 Exp M4 Exp M3

14 ISPD 2000, San DiegoApr 10, 2000 --14-- Model validation (cont.) Experimental validation –adding virtual vias on M3 and M4 (effect of wires on virtual upper layers) Exp M4 Exp M3 Via fill rate (%) Utilization factor (%) Sai-Halasz (M4) Sai-Halasz (M1) Chong Chen Sai-Halasz (M3) Sai-Halasz (M2) 75 65 60 55 50 45 40 35 30 70 Exp M2 0123465

15 ISPD 2000, San DiegoApr 10, 2000 --15-- Model validation (cont.) Predictions for future designs –number of layers >>, die size >> –via impact severely underestimated –predicted limits on number of layers too high Via fill rate (%) Utilization factor (%) Chong Chen 80 70 60 50 40 30 20 10 0 M4 M3 01020304050

16 ISPD 2000, San DiegoApr 10, 2000 --16-- Model validation (cont.) Predictions for future designs LayerChongChenExperiment M17126630973113452 M227562023585 M3009894 M4000 Total9882830973146931 Layers needed224 Number of terminal vias

17 ISPD 2000, San DiegoApr 10, 2000 --17-- Outline Models of achievable routing Review of existing models Validation of models through experiments! Experimental analysis of assumptions Future model requirements Conclusions

18 ISPD 2000, San DiegoApr 10, 2000 --18-- Routing efficiency Constant over all layers? Via fill rate (%) Utilization factor (%) Chong Chen 80 70 60 50 40 30 20 10 0 M4 M3 01020304050

19 ISPD 2000, San DiegoApr 10, 2000 --19-- Routing efficiency Are we measuring routing efficiency or inefficiency? –thought experiment given placement of given netlist route with very good router, measure U i route again with very bad router, measure U i –which one has better routing efficiency? –which one has higher utilization factor? –Give credit for completing nets, not for using metal (use Steiner length instead of actual length for U i )!

20 ISPD 2000, San DiegoApr 10, 2000 --20-- Layer assignment assumptions shorter wires on lower tiers / wires on 1 tier Actual Length (%) Actual Number of Layers Steiner Length (  m)

21 ISPD 2000, San DiegoApr 10, 2000 --21-- Real Wiring Effects Cascade/ripple effect Effect of vias depends on wire length Proposal: l+1 intersections

22 ISPD 2000, San DiegoApr 10, 2000 --22-- Real Wiring Effects (cont.) A simple proposal –probability wire is not blocked: –via impact factor: Via fill rate (%) Utilization factor (%) Chong Chen 80 70 60 50 40 30 20 10 0 M4 M3 01020304050 Model M3Model M4

23 ISPD 2000, San DiegoApr 10, 2000 --23-- Conclusion Better/more accurate models needed –understanding routing efficiency –layer assignment model allows >1 tier/wire –via impact based on real wiring effects wirelength on layer is important cascade/ripple effect Experimental verification of models a must! There is a lot of work yet to be done

24 ISPD 2000, San DiegoApr 10, 2000 --24-- Constant via impact factor Utilization factor constant? LayerSai-HalaszU i /U i+1 M1/M20.850.07 M2/M30.850.56 M3/M40.851.10 M3/M4 Utilization factor ratio Via fill rate (%)

Download ppt "ISPD 2000, San DiegoApr 10, 2000 --1-- Requirements for Models of Achievable Routing Andrew B. Kahng, UCLA Stefanus Mantik, UCLA Dirk Stroobandt, Ghent."

Similar presentations

-1- VLSI CAD Laboratory, UC San Diego Post-Routing BEOL Layout Optimization for Improved Time- Dependent Dielectric Breakdown (TDDB) Reliability Tuck-Boon.

-1- VLSI CAD Laboratory, UC San Diego Post-Routing BEOL Layout Optimization for Improved Time- Dependent Dielectric Breakdown (TDDB) Reliability Tuck-Boon.
Cadence Design Systems, Inc. Why Interconnect Prediction Doesn’t Work.

Cadence Design Systems, Inc. Why Interconnect Prediction Doesn’t Work.
Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.

Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.
Hsi-An Chien Ting-Chi Wang Redundant-Via-Aware ECO Routing ASPDAC2014.

Hsi-An Chien Ting-Chi Wang Redundant-Via-Aware ECO Routing ASPDAC2014.
BSPlace: A BLE Swapping technique for placement 04.09.2014 Minsik Hong George Hwang Hemayamini Kurra Minjun Seo 1.

BSPlace: A BLE Swapping technique for placement Minsik Hong George Hwang Hemayamini Kurra Minjun Seo 1.
Reap What You Sow: Spare Cells for Post-Silicon Metal Fix Kai-hui Chang, Igor L. Markov and Valeria Bertacco ISPD’08, Pages 103-110.

Reap What You Sow: Spare Cells for Post-Silicon Metal Fix Kai-hui Chang, Igor L. Markov and Valeria Bertacco ISPD’08, Pages
Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.

Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.

Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
SLIP 2008, Newcastle Revisiting Fidelity: A Case of Elmore-based Y-routing Trees Tuhina Samanta*, Prasun Ghosal*, Hafizur Rahaman* and Parthasarathi Dasgupta†

SLIP 2008, Newcastle Revisiting Fidelity: A Case of Elmore-based Y-routing Trees Tuhina Samanta*, Prasun Ghosal*, Hafizur Rahaman* and Parthasarathi Dasgupta†
Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu Lim

Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu Lim
DARPA Assessing Parameter and Model Sensitivities of Cycle-Time Predictions Using GTX u Abstract The GTX (GSRC Technology Extrapolation) system serves.

DARPA Assessing Parameter and Model Sensitivities of Cycle-Time Predictions Using GTX u Abstract The GTX (GSRC Technology Extrapolation) system serves.
Toward Better Wireload Models in the Presence of Obstacles* Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu and Dirk Stroobandt† UC San Diego CSE Dept. †Ghent.

Toward Better Wireload Models in the Presence of Obstacles* Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu and Dirk Stroobandt† UC San Diego CSE Dept. †Ghent.
Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength Estimator Andrew B. KahngSherief Reda VLSI CAD Laboratory.

Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength Estimator Andrew B. KahngSherief Reda VLSI CAD Laboratory.
On the Relevance of Wire Load Models Kenneth D. Boese, Cadence Design Systems, San Jose Andrew B. Kahng, UCSD CSE and ECE Depts., La Jolla Stefanus Mantik,

On the Relevance of Wire Load Models Kenneth D. Boese, Cadence Design Systems, San Jose Andrew B. Kahng, UCSD CSE and ECE Depts., La Jolla Stefanus Mantik,
Architectural-Level Prediction of Interconnect Wirelength and Fanout Kwangok Jeong, Andrew B. Kahng and Kambiz Samadi UCSD VLSI CAD Laboratory

Architectural-Level Prediction of Interconnect Wirelength and Fanout Kwangok Jeong, Andrew B. Kahng and Kambiz Samadi UCSD VLSI CAD Laboratory
Study of Floating Fill Impact on Interconnect Capacitance Andrew B. Kahng Kambiz Samadi Puneet Sharma CSE and ECE Departments University of California,

Study of Floating Fill Impact on Interconnect Capacitance Andrew B. Kahng Kambiz Samadi Puneet Sharma CSE and ECE Departments University of California,
On Modeling and Sensitivity of Via Count in SOC Physical Implementation Kwangok Jeong Andrew B. Kahng.

On Modeling and Sensitivity of Via Count in SOC Physical Implementation Kwangok Jeong Andrew B. Kahng.
Dirk Stroobandt Ghent University Electronics and Information Systems Department A Priori System-Level Interconnect Prediction The Road to Future Computer.

Dirk Stroobandt Ghent University Electronics and Information Systems Department A Priori System-Level Interconnect Prediction The Road to Future Computer.
Dirk Stroobandt Ghent University Electronics and Information Systems Department A Priori System-Level Interconnect Prediction The Road to Future Computer.

Dirk Stroobandt Ghent University Electronics and Information Systems Department A Priori System-Level Interconnect Prediction The Road to Future Computer.
1 A Tale of Two Nets: Studies in Wirelength Progression in Physical Design Andrew B. Kahng Sherief Reda CSE Department University of CA, San Diego.

1 A Tale of Two Nets: Studies in Wirelength Progression in Physical Design Andrew B. Kahng Sherief Reda CSE Department University of CA, San Diego.

Similar presentations

Ads by Google