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Gate Sizing for Cell Library Based Designs Shiyan Hu*, Mahesh Ketkar**, Jiang Hu* *Dept of ECE, Texas A&M University **Intel Corporation

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2 Outline Introduction Introduction Motivation Motivation Problem Formulation Problem Formulation Algorithms Algorithms –Continuous solution guided dynamic programming –Node pruning and Stage pruning –Locality Sensitive Hashing based pruning Experimental Results Experimental Results Conclusion Conclusion

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3 Gate Sizing Problem Size a gate Size a gate –Gate power –Driving resistance –Input capacitance Gate sizing problem Gate sizing problem –Minimize power subject to timing constraint Gate sizing for timing- power tradeoff

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4 Continuous Gate Sizing Previous works Previous works –Fishburn and Dunlop, ICCAD85 –Sapatnekar, Rao, Vaidya, and Kang TCAD 93 –Chen, Chu, and Wong, TCAD99 Continuous problem formulation Minimize Area (Power) Subject to: Delay T Delay T X min X X max X min X X max 1 X1X1 X2X2 X3X3 2 3

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5 Motivation Trend: cell library based design Trend: cell library based design –Discrete gate sizes Need to round continuous gate sizes Need to round continuous gate sizes Sparseness of gate library big rounding error Sparseness of gate library big rounding error Timing violation

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6 Nearest Rounding Does Not Work Continuous solution by mathematical programming Continuous solution by mathematical programming Rounding continuous sizes to nearest discrete sizes Rounding continuous sizes to nearest discrete sizes

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7 Discrete Gate Sizing Very few existing approach Very few existing approach GS approach [Coudert, TVLSI97] GS approach [Coudert, TVLSI97] –Trial-and-error style algorithm Based on slacks, pick a group of gates for sizing Based on slacks, pick a group of gates for sizing Random perturbation Random perturbation Repeat until convergence Repeat until convergence –Significant room for improvement

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8 Our Choices Discrete gate sizing is an integer programming problem Discrete gate sizing is an integer programming problem –Hard to solve for large circuits Rounding? Rounding? –Not good solution quality –Very fast Dynamic programming? Dynamic programming? –Best solution quality –Computationally prohibitive

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9 Our Idea Dynamic programming based rounding Dynamic programming based rounding –Continuous solution guided dynamic programming Largely reduce search space Largely reduce search space Keep solution quality Keep solution quality –At each cell, try discrete gate sizes around the obtained continuous size –For critical cells, try more gate sizes

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10 Overall Flow Circuit partitioning Process stage by stage Pick best solutions at PO For each gate, sizing around continuous solution and perform node pruning Locality sensitive hashing based pruning Stage pruning

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11 Circuit Partitioning A cutlineA cutline – prune solutions for acceleration A stage - solution propagation

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12 Dynamic Programming Based Rounding Try gate sizes around continuous solution For timing critical nodes, try more sizes

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13 Pruning For Acceleration Three types of pruning Three types of pruning –Node pruning Inside a stage Inside a stage –Stage pruning At cutline At cutline –Locality Sensitive Hashing based pruning At cutline At cutline

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14 Node Pruning (I) Solution Characterization Solution Characterization –A solution s is characterized by D(s) and W(s). D(s): maximum delay from any primary input to any processed gate D(s): maximum delay from any primary input to any processed gate W(s): cumulative gate area for all processed gates W(s): cumulative gate area for all processed gates Node Pruning Node Pruning –Two solutions s1, s2 s1 is pruned if s1 is pruned if –D(s1) D(s2): larger delay, and –W(s1) W(s2): larger area.

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15 Node Pruning (II) Solution 1: (D,W)=(11,4) Solution 2: (D,W)=(10,3) Pruned D 1x 2x 1x D

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16 Stage Pruning Solution Characterization Solution Characterization –A solution s is characterized by f(s) and W(s). f(s) measures the proximity to the continuous solution f(s) measures the proximity to the continuous solution –gate i : discrete size, gate i c : continuous size W(s): cumulative gate area for all processed gates W(s): cumulative gate area for all processed gates Stage Pruning Stage Pruning –Two solutions s1, s2 s1 is pruned if s1 is pruned if –f(s1) f(s2): farther to continuous solution, and –W(s1) W(s2): larger area.

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17 Locality Sensitive Hashing Based Pruning Maintain diversity in solutions Maintain diversity in solutions –Do not spend time in checking similar solutions How? How? –Cluster solutions –For each cluster, pick a few representative solutions for propagation

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18 Solution Clustering A gate a dimension A gate a dimension Coordinate = gate implementation ID Coordinate = gate implementation ID Large circuit many dimensions Large circuit many dimensions Efficient clustering needed Efficient clustering needed –Most existing approaches does not scale well with dimensionality

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19 Locality Sensitive Hashing For m solutions in d dimensions, clustering runs in only O(dmlogm) time For m solutions in d dimensions, clustering runs in only O(dmlogm) time –Linear in dimension Idea: Idea: –For a solution, concatenate coordinates in all d dimensions to a single string –Map it to a much shorter one while preserving distance properties –Many solutions many short strings. Cluster them.

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20 Solution 1 1x 2x 5x 1, 2, 5 Concatenate discrete gate sizes to form a string 00001,00011,11111 Unary representation

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21 Solution 2 1x 2x 3x 00001,00011,00111 Unary representation 1, 2, 3 Concatenate discrete gate sizes to form a string

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22 Hashing (I) 00001,00011,11111 00001,00011,00111 Randomly pick k=5 locations Solution 1 Solution 2 01011 Solution 1 01001 Solution 2 Shorter strings

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23 Hashing (II) Same shorter strings Hash to same bucket Same shorter strings Hash to same bucket Indyk et al, prove that Indyk et al, prove that –With large probability, geometrically close points are hashed together and geometrically far-apart points are hashes into different buckets. –A bucket = a cluster.

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24 Experimental Setup ISCAS85 benchmark circuits ISCAS85 benchmark circuits X86 computer with 3.2Ghz CPU and 1G memory X86 computer with 3.2Ghz CPU and 1G memory 130nm technology 130nm technology 10 geometrically spaced gate sizes per gate type 10 geometrically spaced gate sizes per gate type Compare to nearest rounding and GS approach Compare to nearest rounding and GS approach

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25 Comparison on Slack and Area Slack for GS: 2ps - 21ps Slack for ours: 1ps - 45ps Area saving ratio over GS Slack from rounding: Slack(ps)Area Reduction

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26 CPU Comparison

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27 Observations Nearest rounding introduces significant timing violations Nearest rounding introduces significant timing violations Our algorithm saves 9%-31% area over GS while still improving slacks in many cases Our algorithm saves 9%-31% area over GS while still improving slacks in many cases Runtime of our algorithm is on average 1.7x of GS. Runtime of our algorithm is on average 1.7x of GS.

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28 Delay-Cost Tradeoff Provide more choices to designers Provide more choices to designers Help users get better timing constraint for circuit Help users get better timing constraint for circuit Two continuous solutions to guide our approach and two curves are obtained Two continuous solutions to guide our approach and two curves are obtained

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29 Conclusion Propose a dynamic programming algorithm for discrete gate sizing problem. Propose a dynamic programming algorithm for discrete gate sizing problem. –Reduce search space by continuous solution guider. –Node pruning, Stage pruning, and Locality Sensitive Hashing based pruning for improving runtime. 9%-31% area reduction compared to GS. 9%-31% area reduction compared to GS. Future work seeks to handling variations in our approach. Future work seeks to handling variations in our approach.

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Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Tel: 310-267-2098 WWW: Copyright 2003.

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