Presentation on theme: "Nios Multi Processor Ethernet Embedded Platform Final Presentation"— Presentation transcript:
1Nios Multi Processor Ethernet Embedded Platform Final Presentation Students:Yevgeny KliteynikOfir CohenInstructor:Yevgeny Fixman
2Abstract Embedded Systems role in the High-Tech world is growing. New embedded systems require a larger amount of flexibility, computation power and reliable I/O devices.This goal can be achieved by using Multi-Processor System with an explicit distribution of tasks.
3Abstract – cont.This way one CPU handles I/O tasks, and the other handles calculation tasks.I/O InterfaceCommonMemoryControllerandArbiterCPU 1ExtensiveCalculationTasksCPU 2I/O
4Abstract – cont.Altera’s embedded processor is a user-configurable, general-purpose RISC embedded processor.Gidel’s development board with an Altera FPGA is a suitable platform for combining System On Chip with peripheral devices.
5Project GoalsCombining Ethernet card with embedded system on Gidel development PCI board.Building Multi-Processor SOC (System On Chip) that consists of two Nios processors with an explicit distribution of tasks:CPU that handles I/O tasks through Ethernet connection.CPU that handles extensive calculation tasks.
6Project Goals – cont.Sharing a common external SDRAM by both Nios CPUs.Writing a software application that demonstrates the concurrent functionality of the system.Building a platform for rapid development of the embedded system on Gidel PCI card using Altera Nios technology.
7Hardware Specifications Proc20K - Gidel PCI development board with:Altera FPGA chip – APEX EP20KOutput voltage 0v – 2.5vInput voltage 0v – 5vFour Micron SDRAM chips – total size 64MBInternal clock – 50MHz, can be configured to 25MHzVoltage supply – 5v, 3.3v and 2.5vEthernet card – Crystal LAN CS8900AConnection speed 10Mb/secInternal oscillator – 20MHzFed by voltage supply of 3.3v
8Hardware Specifications – cont. Ethernet card connectorFed by voltage supply of 3.3vImplementation – pin-to-pin wire-upSerial Port adaptive connectorVoltage converter – MAX232CPEFed by voltage supply of 5vConversion ranges: [-12v, 12v] – [0, 5]System clock ratesNios CPU core – 25MHzMicron SDRAM – 25MHz
10SOC Structure The system consists of number of configurable modules (Altera cores).SystemModulesSDRAMControllerNios CPU(Math)Uart 1EthernetModuleUart 2(E-net)Germs 2Germs 1
11SOC Structure The modules are connected to Avalon Bus that responsible for arbitration of data & instructions flow.SystemModulesSDRAMControllerNios CPU(Math)Uart 1EthernetModuleUart 2(E-net)Germs 2Germs 1AvalonBusridge
12SOC Structure The system contains interface to external devices: SDRAM, Ethernet and Serial port.SystemModulesSDRAMControllerAvalonBusridgeNios CPU(Math)Uart 1EthernetModuleUart 2(E-net)Germs 2Germs 1Ethernet EFSerial IFSDRAM IF
13SOC Structure The Uart Selection logic was added in order to determine the active Uart module.SystemModulesSDRAMControllerAvalonBusridgeNios CPU(Math)Uart 1EthernetModuleUart 2(E-net)Germs 2Germs 1Ethernet IFSerial IFSDRAM IFUartSelectionLogic
14Main SOC Modules A configurable RISC processor that enables SW development for the embedded system. It can beconfigured to suit special design needs.Universal bus that has data and instruction buses.All the other modules are connected to it.A controller with an interface to external SDRAM.Supports number of Nios CPUs that are connectedto the Avalon Bus and performs arbitration of theaccess requests.NiosCPUAvalon BusSDRAMController
15Main SOC Modules – cont.CS8900 module that communicates with the Ethernetcard and supports different communication protocols,such as TCP/IP.A monitor that is responsible for loading of the SWcode into the program memory area of Nios CPU.The SW is received through the Serial port.The module that implements the RS232communication protocol.The logic that makes it possible to select the activeUart module.EthernetModuleGermsUartUartSelectionLogic
16Memory Sharing Both Nios CPUs have access to the same SDRAM. Problem: Memory sharing violation.ProgramMemoryStackDataCommonCPU12ProgramMemoryStackDataSolution: Dividing memory address space to separate areas – common and private.
17Peripheral Devices The system should use an external Ethernet card. Problem: the Ethernet card and Gidel board have different physical structure.Solution: Adaptive connector for the Ethernet card fed by voltage of 3.3v from the PCI board.
18Peripheral Devices – cont. The SW that should run on each Nios CPU is uploadedfrom the PC to the Germs monitor through Serial port.Problems:Gidel PCI board doesn’t have a suitable connector.PC serial port operates in voltage range -12v - +12v while FPGA chip supplies 0v – 2.5v and receives voltage 0v – 5v.Solution: Adapter for the serial connector that contains voltage converter fed by voltage of 5v from the PCI board.
19SoftwareSW Application was written to demonstrate the parallel operation of the system.Nios CPUs roles in the application:I/O CPU, where I/O device is Ethernet cardCPU for mathematical calculations.The application implements cracking Diffie-Helmman protocol of symmetrical encryption.
20Software – The Application Flow Transferring InputsthroughTelnet ConnectionTransferring InputsthroughCommon Area of SDRAMNiosE-net CPUCalculatingtheResultUser(TelnetClient)NiosMath CPUNiosE-net CPUTransferring ResultthroughCommon Area of SDRAMTransferring ResultthroughTelnet Connection
21Software – Timing Protocol The application requires transferring data betweenthe CPUs – user input transferred from the EthernetCPU to the math. CPU and result is transferred in theopposite direction.Problem: Common memory access timing.Check FetchFlag – Fetch dataand calculateTransferred user inputsFlagTransferred ResultandSet Ready FlagCheck ReadyFlag and fetch the ResultSolution: Timing protocol.
22Software – Debugging The application development required significant debugging efforts.The debugging was done through:External registers: Nios CPUs can read/write to these registers, and they are also accessible through ProcWizard program.Serial Port: it is possible to print messages to screen when connected to the Serial Port in Nios Terminal Mode.
23Conclusion NotesBuilt a flexible Multi-Processor embedded System that consists of two processors with an explicit distribution of tasks.Written a software application that demonstrates the parallel functionality of the system.Developed Embedded System platform that can be used in future projects.The system can be used as a platform for development of parallel applications.