1. Nios Multi Processor Ethernet Embedded Platform Final Presentation
Students:
Yevgeny Kliteynik
Ofir Cohen
Instructor:
Yevgeny Fixman

2. Abstract Embedded Systems role in the High-Tech world is growing.
New embedded systems require a larger amount of flexibility, computation power and reliable I/O devices.
This goal can be achieved by using Multi-Processor System with an explicit distribution of tasks.

3. Abstract – cont.
This way one CPU handles I/O tasks, and the other handles calculation tasks.
I/O Interface
Common
Memory
Controller
and
Arbiter
CPU 1
Extensive
Calculation
Tasks
CPU 2
I/O

4. Abstract – cont.
Altera’s embedded processor is a user-configurable, general-purpose RISC embedded processor.
Gidel’s development board with an Altera FPGA is a suitable platform for combining System On Chip with peripheral devices.

5. Project Goals
Combining Ethernet card with embedded system on Gidel development PCI board.
Building Multi-Processor SOC (System On Chip) that consists of two Nios processors with an explicit distribution of tasks:
CPU that handles I/O tasks through Ethernet connection.
CPU that handles extensive calculation tasks.

6. Project Goals – cont.
Sharing a common external SDRAM by both Nios CPUs.
Writing a software application that demonstrates the concurrent functionality of the system.
Building a platform for rapid development of the embedded system on Gidel PCI card using Altera Nios technology.

7. Hardware Specifications
Proc20K - Gidel PCI development board with:
Altera FPGA chip – APEX EP20K
Output voltage 0v – 2.5v
Input voltage 0v – 5v
Four Micron SDRAM chips – total size 64MB
Internal clock – 50MHz, can be configured to 25MHz
Voltage supply – 5v, 3.3v and 2.5v
Ethernet card – Crystal LAN CS8900A
Connection speed 10Mb/sec
Internal oscillator – 20MHz
Fed by voltage supply of 3.3v

8. Hardware Specifications – cont.
Ethernet card connector
Fed by voltage supply of 3.3v
Implementation – pin-to-pin wire-up
Serial Port adaptive connector
Voltage converter – MAX232CPE
Fed by voltage supply of 5v
Conversion ranges: [-12v, 12v] – [0, 5]
System clock rates
Nios CPU core – 25MHz
Micron SDRAM – 25MHz

9. System Overview SDRAM Gidel PCI Card PLX Apex FPGA Ethernet Card
PCI IF
SDRAM
Controller
Nios CPU
(Math)
Germs
(E-net)
Uart
Selection
Serial Port
Connector
Ethernet
Card
Serial IF
E-net IF
Adaptive
Connector

10. SOC Structure The system consists of number of configurable
modules (Altera cores).
System
Modules
SDRAM
Controller
Nios CPU
(Math)
Uart 1
Ethernet
Module
Uart 2
(E-net)
Germs 2
Germs 1

11. SOC Structure The modules are connected to Avalon Bus that
responsible for arbitration of data & instructions flow.
System
Modules
SDRAM
Controller
Nios CPU
(Math)
Uart 1
Ethernet
Module
Uart 2
(E-net)
Germs 2
Germs 1 A v a l o n B u s r i d g e

12. SOC Structure The system contains interface to external devices:
SDRAM, Ethernet and Serial port.
System
Modules
SDRAM
Controller A v a l o n B u s r i d g e
Nios CPU
(Math)
Uart 1
Ethernet
Module
Uart 2
(E-net)
Germs 2
Germs 1
Ethernet EF
Serial IF
SDRAM IF

13. SOC Structure The Uart Selection logic was added in order to
determine the active Uart module.
System
Modules
SDRAM
Controller A v a l o n B u s r i d g e
Nios CPU
(Math)
Uart 1
Ethernet
Module
Uart 2
(E-net)
Germs 2
Germs 1
Ethernet IF
Serial IF
SDRAM IF
Uart
Selection
Logic

14. Main SOC Modules A configurable RISC processor that enables SW
development for the embedded system. It can be
configured to suit special design needs.
Universal bus that has data and instruction buses.
All the other modules are connected to it.
A controller with an interface to external SDRAM.
Supports number of Nios CPUs that are connected
to the Avalon Bus and performs arbitration of the
access requests.
Nios
CPU
Avalon Bus
SDRAM
Controller

15. Main SOC Modules – cont.
CS8900 module that communicates with the Ethernet
card and supports different communication protocols,
such as TCP/IP.
A monitor that is responsible for loading of the SW
code into the program memory area of Nios CPU.
The SW is received through the Serial port.
The module that implements the RS232
communication protocol.
The logic that makes it possible to select the active
Uart module.
Ethernet
Module
Germs
Uart
Uart
Selection
Logic

16. Memory Sharing Both Nios CPUs have access to the same SDRAM.
Problem: Memory sharing violation.
Program
Memory
Stack
Data
Common C P U 1 2
Program
Memory
Stack
Data
Solution: Dividing memory address space to separate areas – common and private.

17. Peripheral Devices The system should use an external Ethernet card.
Problem: the Ethernet card and Gidel board have different physical structure.
Solution: Adaptive connector for the Ethernet card fed by voltage of 3.3v from the PCI board.

18. Peripheral Devices – cont.
The SW that should run on each Nios CPU is uploaded
from the PC to the Germs monitor through Serial port.
Problems:
Gidel PCI board doesn’t have a suitable connector.
PC serial port operates in voltage range -12v - +12v while FPGA chip supplies 0v – 2.5v and receives voltage 0v – 5v.
Solution: Adapter for the serial connector that contains voltage converter fed by voltage of 5v from the PCI board.

19. Software
SW Application was written to demonstrate the parallel operation of the system.
Nios CPUs roles in the application:
I/O CPU, where I/O device is Ethernet card
CPU for mathematical calculations.
The application implements cracking Diffie-Helmman protocol of symmetrical encryption.

20. Software – The Application Flow
Transferring Inputs
through
Telnet Connection
Transferring Inputs
through
Common Area of SDRAM
Nios
E-net CPU
Calculating
the
Result
User
(Telnet
Client)
Nios
Math CPU
Nios
E-net CPU
Transferring Result
through
Common Area of SDRAM
Transferring Result
through
Telnet Connection

21. Software – Timing Protocol
The application requires transferring data between
the CPUs – user input transferred from the Ethernet
CPU to the math. CPU and result is transferred in the
opposite direction.
Problem: Common memory access timing.
Check Fetch
Flag – Fetch data
and calculate
Transferred user inputs
Flag
Transferred Result
and
Set Ready Flag
Check Ready
Flag and fetch the Result
Solution: Timing protocol.

22. Software – Debugging The application development required significant
debugging efforts.
The debugging was done through:
External registers: Nios CPUs can read/write to these registers, and they are also accessible through ProcWizard program.
Serial Port: it is possible to print messages to screen when connected to the Serial Port in Nios Terminal Mode.

23. Conclusion Notes
Built a flexible Multi-Processor embedded System that consists of two processors with an explicit distribution of tasks.
Written a software application that demonstrates the parallel functionality of the system.
Developed Embedded System platform that can be used in future projects.
The system can be used as a platform for development of parallel applications.

24. The End