Presentation on theme: "Nios Multi Processor Ethernet Embedded Platform Nios Multi Processor Ethernet Embedded Platform Final Presentation Students: Yevgeny Kliteynik Ofir Cohen."— Presentation transcript:
Nios Multi Processor Ethernet Embedded Platform Nios Multi Processor Ethernet Embedded Platform Final Presentation Students: Yevgeny Kliteynik Ofir Cohen Instructor: Yevgeny Fixman
Abstract Embedded Systems role in the High-Tech world is growing. New embedded systems require a larger amount of flexibility, computation power and reliable I/O devices. This goal can be achieved by using Multi-Processor System with an explicit distribution of tasks.
Abstract – cont. This way one CPU handles I/O tasks, and the other handles calculation tasks. I/O Interface Common Memory Controller and Arbiter CPU 1 Extensive Calculation Tasks CPU 2 I/O Tasks
Abstract – cont. Alteras embedded processor is a user-configurable, general-purpose RISC embedded processor. Gidels development board with an Altera FPGA is a suitable platform for combining System On Chip with peripheral devices.
Project Goals Combining Ethernet card with embedded system on Gidel development PCI board. Building Multi-Processor SOC (System On Chip) that consists of two Nios processors with an explicit distribution of tasks: CPU that handles I/O tasks through Ethernet connection. CPU that handles extensive calculation tasks.
Project Goals – cont. Sharing a common external SDRAM by both Nios CPUs. Writing a software application that demonstrates the concurrent functionality of the system. Building a platform for rapid development of the embedded system on Gidel PCI card using Altera Nios technology.
Hardware Specifications Proc20K - Gidel PCI development board with: Altera FPGA chip – APEX EP20K Output voltage 0v – 2.5v Input voltage 0v – 5v Four Micron SDRAM chips – total size 64MB Internal clock – 50MHz, can be configured to 25MHz Voltage supply – 5v, 3.3v and 2.5v Ethernet card – Crystal LAN CS8900A Connection speed 10Mb/sec Internal oscillator – 20MHz Fed by voltage supply of 3.3v
Hardware Specifications – cont. Ethernet card connector Fed by voltage supply of 3.3v Implementation – pin-to-pin wire-up Serial Port adaptive connector Voltage converter – MAX232CPE Fed by voltage supply of 5v Conversion ranges: [-12v, 12v] – [0, 5] System clock rates Nios CPU core – 25MHz Micron SDRAM – 25MHz
Gidel PCI Card Apex FPGA SDRAM PLX PCI IF System Overview Adaptive Connector SDRAM Controller Nios CPU (Math) Germs Nios CPU (E-net) Germs Uart Selection Serial Port Connector Ethernet Card Serial IF E-net IF
SOC Structure System Modules SDRAM Controller Nios CPU (Math) Uart 1 Ethernet Module Uart 2 Nios CPU (E-net) Germs 2Germs 1 The system consists of number of configurable modules (Altera cores).
System Modules SDRAM Controller Nios CPU (Math) Uart 1 Ethernet Module Uart 2 Nios CPU (E-net) Germs 2Germs 1 SOC Structure A v a l o n B u s BridgeBridge The modules are connected to Avalon Bus that responsible for arbitration of data & instructions flow.
System Modules SDRAM Controller A v a l o n B u s BridgeBridge Nios CPU (Math) Uart 1 Ethernet Module Uart 2 Nios CPU (E-net) Germs 2Germs 1 SOC Structure Ethernet EF Serial IF SDRAM IF The system contains interface to external devices: SDRAM, Ethernet and Serial port.
System Modules SDRAM Controller A v a l o n B u s BridgeBridge Nios CPU (Math) Uart 1 Ethernet Module Uart 2 Nios CPU (E-net) Germs 2Germs 1 Ethernet IF Serial IF SDRAM IF SOC Structure Uart Selection Logic The Uart Selection logic was added in order to determine the active Uart module.
SDRAM Controller Nios CPU Main SOC Modules A configurable RISC processor that enables SW development for the embedded system. It can be configured to suit special design needs. Universal bus that has data and instruction buses. All the other modules are connected to it. A controller with an interface to external SDRAM. Supports number of Nios CPUs that are connected to the Avalon Bus and performs arbitration of the access requests. Avalon Bus
Uart Ethernet Module Germs Main SOC Modules – cont. Uart Selection Logic CS8900 module that communicates with the Ethernet card and supports different communication protocols, such as TCP/IP. A monitor that is responsible for loading of the SW code into the program memory area of Nios CPU. The SW is received through the Serial port. The module that implements the RS232 communication protocol. The logic that makes it possible to select the active Uart module.
Memory Sharing Both Nios CPUs have access to the same SDRAM. Problem: Memory sharing violation. Program Memory Stack Memory Data Memory Program Memory Stack Memory Data Memory Program Memory Stack Memory Data Memory Common CPU1CPU1 CPU2CPU2 Solution: Dividing memory address space to separate areas – common and private.
Peripheral Devices The system should use an external Ethernet card. Problem: the Ethernet card and Gidel board have different physical structure. Solution: Adaptive connector for the Ethernet card fed by voltage of 3.3v from the PCI board.
Peripheral Devices – cont. The SW that should run on each Nios CPU is uploaded from the PC to the Germs monitor through Serial port. Problems: Gidel PCI board doesnt have a suitable connector. PC serial port operates in voltage range -12v - +12v while FPGA chip supplies 0v – 2.5v and receives voltage 0v – 5v. Solution: Adapter for the serial connector that contains voltage converter fed by voltage of 5v from the PCI board.
Software SW Application was written to demonstrate the parallel operation of the system. Nios CPUs roles in the application: I/O CPU, where I/O device is Ethernet card CPU for mathematical calculations. The application implements cracking Diffie-Helmman protocol of symmetrical encryption.
Software – The Application Flow Calculating the Result Transferring Inputs through Telnet Connection Nios E-net CPU Nios Math CPU Transferring Inputs through Common Area of SDRAM Transferring Result through Common Area of SDRAM Nios E-net CPU Transferring Result through Telnet Connection User (Telnet Client)
Software – Timing Protocol The application requires transferring data between the CPUs – user input transferred from the Ethernet CPU to the math. CPU and result is transferred in the opposite direction. Problem: Common memory access timing. Check Fetch Flag – Fetch data and calculate Transferred user inputs Check Fetch Flag Transferred Result and Set Ready Flag Check Ready Flag and fetch the Result Solution: Timing protocol.
Software – Debugging The application development required significant debugging efforts. The debugging was done through: External registers: Nios CPUs can read/write to these registers, and they are also accessible through ProcWizard program. Serial Port: it is possible to print messages to screen when connected to the Serial Port in Nios Terminal Mode.
Conclusion Notes Built a flexible Multi-Processor embedded System that consists of two processors with an explicit distribution of tasks. Written a software application that demonstrates the parallel functionality of the system. Developed Embedded System platform that can be used in future projects. The system can be used as a platform for development of parallel applications.