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Synplify Global Clock Resource Attributes December 2013 Tecnomic Bangalore.

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Presentation on theme: "Synplify Global Clock Resource Attributes December 2013 Tecnomic Bangalore."— Presentation transcript:

1 Synplify Global Clock Resource Attributes December 2013 Tecnomic Bangalore

2 Proasic3 Devices has 6 Global Resources available Synplify Will promote the signals based on the fan-out of the signal Different signal has different fan-out threshold for global promotion Clock nets2 Asynchronous set/reset12 Data nets5000 You can change the threshold in the Synplify settings

3 Types of Control is available 1.Enable Only Specific signal to be promoted 2.Disable Only Specific Signal from Promoted 3.Disable All Global Promotion

4 syn_insert_buffer attribute This method will allow a specific signal to be promoted to the global resource This can override the default fan-out guide as well The below example will promote Port CLK to a global resource define_attribute {clk} {syn_insert_buffer} {CLKBUF}

5 syn_noclockbuf attribute This method will disbale the specific signal from promoted to the global resource The below example will disable Aclr port from using the Global resource define_attribute {aclr} {syn_noclockbuf} {1}

6 syn_noclockbuf ( define_global ) attribute Use the syn_noclockbuf attribute with the global reach to achieve the same All the signals will be buffered using regular buffer Specific signal can be promoted to the Global using the other attribute define_global_attribute syn_noclockbuf {1}

7 First Synthesis the Design to Find the High Fan-out Nets Look under the High Fan-out nets section in synplify log file Following signal are promoted to global aclr -- aclr_c clk -- clk_c enable -- enable_c clk2 -- un2_clk2 Synplify log file High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes un2_clk2 / Y 71 aclr_pad / Y 158 : 158 asynchronous set/reset enable_pad / Y 142 ====================================================== : | Promoting Net aclr_c on CLKBUF : | Promoting Net enable_c on CLKINT : | Promoting Net clk_c on CLKBUF : | Promoting Net un2_clk2 on CLKINT I_142 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication

8 Create a new sdc file in Libero Use the syn_noclockbuf attibute Add to synthesis project when invoking synplify from libero Counter.sdc ## counter.sdc ## Disable Global Buffer Promotion for Entire design, ## No Global Buffer will be used by Default define_global_attribute syn_noclockbuf {1}

9 No Global Buffer used All the 4 Signals are buffered using regular Buffers Some Signals will be replicated 6 regular buffers used in this design ( 0 buffers without the attibute Synplify Log file High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes un2_clk2 / Y 71 aclr_pad / Y 158 : 158 asynchronous set/reset enable_pad / Y 142 ========================================================== Buffering enable_c, fanout 142 segments 3 Buffering clk_c, fanout 87 segments 2 Buffering aclr_c, fanout 158 segments 4 Replicating Combinational Instance un2_clk2, fanout 71 segments 2 Added 6 Buffers Added 1 Cells via replication Added 0 Sequential Cells via replication Added 1 Combinational Cells via replication

10 This time clk signal being promoted to Global All other signals remains same Signal CLK is missing from the buffer tree this time counter.sdc define_global_attribute syn_noclockbuf {1} define_attribute {clk} {syn_insert_buffer} {CLKBUF} Synplify log file High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes un2_clk2 / Y 71 aclr_pad / Y 158 : 158 asynchronous set/reset enable_pad / Y 142 ================================================== Buffering enable_c, fanout 142 segments 3 Buffering aclr_c, fanout 158 segments 4 Replicating Combinational Instance un2_clk2, fanout 71 segments 2 Added 5 Buffers Added 1 Cells via replication Added 0 Sequential Cells via replication Added 1 Combinational Cells via replication Synplify log file ###########################################################] Premap Report Adding property syn_noclockbuf, value 1 to view:work.counter(one)

11 restrict aclr from being promoted to global All other signal can be promoted to global depending on the fan-out Note that the global restriction constraint is commented(#) and not used Synplify log file High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes un2_clk2 / Y 71 aclr_pad / Y 158 : 158 asynchronous set/reset enable_pad / Y 142 ========================================================== : | Promoting Net enable_c on CLKINT : | Promoting Net clk_c on CLKBUF : | Promoting Net un2_clk2 on CLKINT I_142 Buffering aclr_c, fanout 158 segments 4 Added 3 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication #define_global_attribute syn_noclockbuf {1} # Disable Global Buffer Promotion for aclr Signal define_attribute {aclr} {syn_noclockbuf} {1} counter.sdc

12 .sdc file method may not work for internal signal Use the attribute in hdl file Example shows restricting clk2 disabled from promoting Counter.vhd High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes un2_clk2 / Y 71 aclr_pad / Y 158 : 158 asynchronous set/reset enable_pad / Y 142 ====================================================== : | Promoting Net enable_c on CLKINT : | Promoting Net clk_c on CLKBUF clk_pad Buffering aclr_c, fanout 158 segments 4 Replicating Combinational Instance un2_clk2, fanout 71 segments 2 Added 3 Buffers Added 1 Cells via replication Added 0 Sequential Cells via replication Added 1 Combinational Cells via replication Counter.vhd signal qaux2 : std_logic_vector(15 downto 0); signal clk2 : std_logic; attribute syn_noclockbuf : boolean; attribute syn_noclockbuf of clk2 : signal is true; begin

13 .sdc file method may not work for internal signal Use the attribute in hdl file Example shows promoting clk2 to global All other signals are restricted using the global constraint in sdc file Synplify log file High Fanout Net Report ********************** Driver Instance / Pin Name Fanout, notes un2_clk2 / Y 71 aclr_pad / Y 158 : 158 asynchronous set/reset enable_pad / Y 142 : | Promoting Net clk2 on CLKINT clk2 Buffering enable_c, fanout 142 segments 3 Buffering clk_c, fanout 87 segments 2 Buffering aclr_c, fanout 158 segments 4 Added 6 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Counter.vhd signal qaux2 : std_logic_vector(15 downto 0); signal clk2 : std_logic; attribute syn_insert_buffer : string; attribute syn_insert_buffer of clk2 : signal is "CLKINT"; begin Counter.sdc ## All signals are barred from being promoted to global define_global_attribute syn_noclockbuf {1}


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