2 Modeling Digital Systems We use VHDL to implement system modelsFor this class you will use simulation to test the correctness of modelsThe design process will be:Develop a design to meet the problem specificationImplement the design using VHDLImplement a simulation testbench to test the correctness of your design and implementation
3 Entity DeclarationSay we want to design a 4-bit register, with enable and clock. We could do this 2 different ways:1244d0q0dqd1q1d2q2d3q3enenclkclk
4 Design 1: entity reg4 is Design 2: port(d0,d1,d2,d3,en,clk: in std_logic;q0,q1,q2,q : out std_logic);end entity reg4;Design 2:port(d : in std_logic_vector(3 downto 0);en, clk : in std_logic;q : out std_logic_vector(3 downto 0));
5 ArchitecturesThe architecture contains the implementation for the entityThere can be multiple architectures per entityBehavioral Architecture--Description of the algorithmThey are made up of processes, which contain sequential statementsSequential statements include signal assignments and wait statements
6 Behavioral Architecture for Design 1 architecture beh of reg4 isbeginupdate: process (d0,d1,d2,d3,en,clk) is-- if register is enabled, and rising-edge clock, update outputsif en=‘1’ and clk=‘1’ and clk’event thenq0<=d0;q1<=d1;q2<=d2;q3<=d3;end if;end process update;end architecture beh;
7 Notes on Behavioral Architectures Signals – wires; concurrent assignmentq0<=d0; these happen at the same timeq1<=d1;Variables – State; sequential assignmentvar1:=d0; these happen sequentialvar2:=var1 or ‘1’; there is state (memory) associated with the variablesInternal signals declared at top of architectureInternal variables declared at top of process
8 Structural Architectures Think of this as building an architecture using existing building-blocks, and connecting the signals. We could make our 4-bit register out of 4 flip-flops:Can you think of ways using gates to implement enable? What if we wanted to add a reset?dod qclkqod1d qclkq1d2q2d qclkd3q3d qclkclk
9 Structural Architecture implementation Say we have already implemented the entity d_latch with architecture beh (with input bits d,clk; output bit q),We also have the entitiy and2 (an and gate), with architecture beh.We will and the clock with enable to send to the clk input of each gate (note: it is not an ideal design to send your clock through logic gates).
10 architecture struct of reg4 is signal internal_clk : std_logic; -- Note: no direction(in/out) for internal signalsbeginbit0: entity work.d_latch(beh)port map(d0,int_clk,q0);bit1: entity work.d_latch(beh))port map(d1,int_clk,q1)clock: entity work.and2port map(clk,en,int_clk);end struct;
11 Notes on Structural Architectures There should be NO processesThe port maps tell you what signals in your structural architecture gets mapped to the signals in the entities. You may be mapping port signals or internal signals. Make sure you order them correctly. Let’s look at the latch entity compared to the first instantiations of a latch in the architecture:d_latch entity declaration:entity d_latch isport (d,clk : in std_logic;q : out std_logic);end entity d_latch;d_latch instantiationbit0: entity work.d_latch(beh)port map(d0,int_clk,q0);So, here we are saying d0 goes to the input d, int_clk goes to the input clk, and q0 goes to the ouput q.
12 Mixed Behavioral and Structural A mixed architecture will have instantiated components and behavioral processes.
13 Test Benches Test benches help determine the correctness of a design. The steps of a testbench are:Instantiate the component(s) to be testedDrive the components’ signalsWaitLook at the waveforms generated by the testbench to determine if the design is correct (note: some problems might be with the testbench, and not the original design)
14 Example Testbench entity tb is -- Note: there are no signal ports end entity tb;architecture test_reg4 of tb is-- all port signals from component under test are now internal signalssignal d0,d1,d2,d3,en,clk,q0,q1,q2,q3: std_logic;begin-- instantiate component(s) under test-- (dut stands for device under test - name doesn’t matter)dut: entity work.reg4(beh) -- this means pick the beh architecture to testport map(d0,d1,d2,d3,en,clk,q0,q1,q2,q3);drive: process isd0<='1'; d1<='1'; d2<='1'; d3<='1'; wait for 20 ns; -- nothing changes, because en!=1en <= '1';d0<='0'; d1<='1'; d2<='0'; d3<='1'; wait for 20 ns; -- output should change nowd0<='1'; d1<='0'; d2<='1'; d3<='0'; wait for 20 ns;wait; -- This wait is very important. This is what will stop your simulation.-- It should be at the end of every testbench processend process drive;clock: process isfor i in 0 to 10 loopclk <= '0'; wait for 5 ns;clk <= '1'; wait for 5 ns;end loop;wait;end process clock;end test_reg4;