Download presentation

Presentation is loading. Please wait.

Published byKaelyn Newey Modified over 2 years ago

1
Lecture #28 Page 1 ECE 4110– Sequential Logic Design Lecture #28 Agenda 1.Counters Announcements 1.HW #13 assigned 2.Next: Test #2 Review

2
Lecture #28 Page 2 Counters Counters in VHDL - strong type casting in VHDL can make modeling counters difficult (at first glance) - the reason for this is that the STANDARD and STD_LOGIC Packages do not define "+", "-", or inequality operators for BIT_VECTOR or STD_LOGIC_VECTOR types

3
Lecture #28 Page 3 Counters Counters in VHDL - there are a couple ways that we get around this 1) Use the STD_LOGIC_UNSIGNED Package - this package defines "+" and "-" functions for STD_LOGIC_VECTOR - we can use +1 just like normal - the vector will wrap as suspected (1111 - 0000) - one catch is that we can't assign to a Port - we need to create an internal signal of STD_LOGIC_VECTOR for counting - we then assign to the Port at the end

4
Lecture #28 Page 4 Counters Counters in VHDL using STD_LOGIC_UNSIGNED use IEEE.STD_LOGIC_UNSIGNED.ALL; -- call the package entity counter is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Direction : in STD_LOGIC; Count_Out : out STD_LOGIC_VECTOR (3 downto 0)); end counter;

5
Lecture #28 Page 5 Counters Counters in VHDL using STD_LOGIC_UNSIGNED architecture counter_arch of counter is signal count_temp : std_logic_vector(3 downto 0);-- Notice internal signal begin process (Clock, Reset) begin if (Reset = '0') then count_temp <= "0000"; elsif (Clock='1' and Clock'event) then if (Direction='0') then count_temp <= count_temp + '1'; -- count_temp can be used on both LHS and RHS else count_temp <= count_temp - '1'; end if; end process; Count_Out <= count_temp; -- assign to Port after the process end counter_arch;

6
Lecture #28 Page 6 Counters Counters in VHDL 2) Use integers for the counter and then convert back to STD_LOGIC_VECTOR - STD_LOGIC_ARITH is a Package that defines a conversion function - the function is: conv_std_logic_vector (ARG, SIZE) - functions are defined for ARG = integer, unsigned, signed, STD_ULOGIC - SIZE is the number of bits in the vector to convert to, given as an integer - we need to keep track of the RANGE and Counter Overflow

7
Lecture #28 Page 7 Counters Counters in VHDL using STD_LOGIC_ARITH use IEEE.STD_LOGIC_ARITH.ALL; -- call the package entity counter is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Direction : in STD_LOGIC; Count_Out : out STD_LOGIC_VECTOR (3 downto 0)); end counter;

8
Lecture #28 Page 8 Counters Counters in VHDL using STD_LOGIC_ARITH architecture counter_arch of counter is signal count_temp : integer range 0 to 15;-- Notice internal integer specified with Range begin process (Clock, Reset) begin if (Reset = '0') then count_temp <= 0; -- integer assignment doesn't requires quotes elsif (Clock='1' and Clock'event) then if (count_temp = 15) then count_temp <= 0; -- we manually check for overflow else count_temp <= count_temp + 1; end if; end process; Count_Out <= conv_std_logic_vector (count_temp, 4);-- convert integer into a 4-bit STD_LOGIC_VECTOR end counter_arch;

9
Lecture #28 Page 9 Counters Counters in VHDL 3) Use UNSIGNED data types #'s - STD_LOGIC_ARITH also defines "+", "-", and equality for UNSIGNED types - UNSIGNED is a Data type defined in STD_LOGIC_ARITH - UNSIGNED is an array of STD_LOGIC - An UNSIGNED type is the equivalent to a STD_LOGIC_VECTOR type - the equality operators assume it is unsigned (as opposed to 2's comp SIGNED) Pro's and Cons - using integers allows a higher level of abstraction and more functionality can be included - easier to write unsynthesizable code or code that produces unwanted logic - both are synthesizable when written correctly

10
Lecture #28 Page 10 Counters Ring Counters in VHDL - to mimic the shift register behavior, we need access to the signal value before and after clock'event - consider the following concurrent signal assignments: architecture …. begin Q0 <= Q3; Q1 <= Q0; Q2 <= Q1; Q3 <= Q2; end architecture… - since they are executed concurrently, it is equivalent to Q0=Q1=Q2=Q3, or a simple wire

11
Lecture #28 Page 11 Counters Ring Counters in VHDL - since a process doesn't assign the signal values until it suspends, we can use this to model the "before and after" behavior of a clock event. process (Clock, Reset) begin if (Reset = '0') then Q0<='1'; Q1<='0';Q2<='0'; Q3<='0'; elsif (Clock'event and Clock='1') then Q0<=Q3;Q1<=Q0;Q2<=Q1;Q3<=Q2; end if; end process - notice that the signals DO NOT appear in the sensitivity list. If they did the process would continually execute and not be synthesized as a flip-flop structure

12
Lecture #28 Page 12 Counters Johnson Counters in VHDL process (Clock, Reset) begin if (Reset = '0') then Q0<='0'; Q1<='0';Q2<='0'; Q3<='0'; elsif (Clock'event and Clock='1') then Q0<=not Q3;Q1<=Q0;Q2<=Q1;Q3<=Q2; end if; end process

13
Lecture #28 Page 13 Counters Linear Feedback Shift Register Counters in VHDL process (Clock, Reset) begin if (Reset = '0') then Q0<='0'; Q1<='0';Q2<='0'; Q3<='0'; elsif (Clock'event and Clock='1') then Q0<=Q3 xor Q2;Q1<=Q0;Q2<=Q1;Q3<=Q2; end if; end process

14
Lecture #28 Page 14 Counters Multiple Processes - we can now use State Machines to control the start/stop/load/reset of counters - each are independent processes that interact with each other through signals - a common task for a state machine is: 1) at a certain state, load and enable a counter 2) go to a state and wait until the counter reaches a certain value 3) when it reaches the certain value, disable the counter and continue to the next state - since the counter runs off of a clock, we know how long it will count between the start and stop

Similar presentations

Presentation is loading. Please wait....

OK

arquitectura – implementação

arquitectura – implementação

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on video teleconferencing systems Ppt on water pollution management Ppt on power grid failure movie Convert doc file to ppt online Ppt on traction rolling stock manufacturers Ppt on any one mathematician turing Ppt on business plan presentation Ppt on diode as rectifier transformer Ppt on developing leadership skills Ppt on conservation of momentum and energy