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Power Delivery Network Optimization for Low Power SoC Anil Gundurao Melinda Yang Eileen You Harpreet Gill System LSI SoC Bay Area R&D Samsung Semiconductor.

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Presentation on theme: "Power Delivery Network Optimization for Low Power SoC Anil Gundurao Melinda Yang Eileen You Harpreet Gill System LSI SoC Bay Area R&D Samsung Semiconductor."— Presentation transcript:

1 Power Delivery Network Optimization for Low Power SoC Anil Gundurao Melinda Yang Eileen You Harpreet Gill System LSI SoC Bay Area R&D Samsung Semiconductor Inc.

2 Samsung Confidential SoC Power Integrity Challenges  28nm SoC flip chip package  10M+ instances, 500+ macros  3 operating voltages  50+ clock domains  Complexity of simulating PDN  SoC complexity: Size, Modes/corners, voltage domains  System complexity: Board and Package  Early analysis and optimizations  Model, Analyze and Optimize  System PI analysis  Add more detailed models in phases PCB Package Die VRM Decaps Decap

3 Samsung Confidential Early System ModelSignoff Model BoardLumped RLCFull Wave PackageLumped RLCFull Wave ChipChip power modelPhysical database Pkg Decap

4 Samsung Confidential Generating chip model  Estimate chip impedance  Intrinsic and Intentional decap  Estimate Rdie / Cdie at operating frequencies Operating freq

5 Samsung Confidential Board + Pkg (embedded decap) + Die Board + Pkg (substrate only) + Die Die + Pkg (with embedded decap) Die + Pkg (Substrate only) Z11 Plots Comparison Board LC Decap Self-resonance  Adding board model changes the Z11 plots  Impact on time-domain noise depends on freq content Frequency Impedance BoardR Lpkg Cdie

6 Samsung Confidential Understanding Current Signature  Demand current = f (circuit switching activity)  FFT (current) Energy concentrated at harmonics of 50MHz Energy concentrated > 500MHz FFT up to 500MHz Mode 2 FFT up to 3GHz Mode 1

7 Samsung Confidential Optimization: Impact of PDN components  Adding on-chip decaps  Changing Package model  Adding embedded decaps  Updating board Model -- Board + Pkg (embed decap) -- Pkg (no decap) -- Board+ Pkg (no decap) -- Pkg (embed decap) Voltage at Pads Sim Time

8 Samsung Confidential Impact of On-chip Decap on DvD

9 Samsung Confidential On-Chip Decap & Package Core Thickness Impact

10 Samsung Confidential Impact of Package and Board impedance  Including Board impedance impacts DvD results  Having Package/ Board decaps will also impact DvD

11 Samsung Confidential Summary  For Power Integrity verification:  Critical to model all components of the system PDN  Time-domain and Frequency domain analysis  Model the system early  Estimated and lumped models to predict the PDN response  Use the system model to study effects of different PDN parameters. Compare Detailed DVD Database


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