Presentation on theme: "Power Delivery Network Optimization for Low Power SoC"— Presentation transcript:
1Power Delivery Network Optimization for Low Power SoC Anil GunduraoMelinda YangEileen YouHarpreet GillSystem LSI SoC Bay Area R&DSamsung Semiconductor Inc.This presentation talks about the analysis and optimization of the power delivery network for low power SoC.It is based on authors’ experience on designing advanced Low power Mobile and Server chips at Samsung Semiconductor Inc.
2SoC Power Integrity Challenges 28nm SoC flip chip package10M+ instances, 500+ macros3 operating voltages50+ clock domainsComplexity of simulating PDNSoC complexity: Size, Modes/corners, voltage domainsSystem complexity: Board and PackageEarly analysis and optimizationsModel, Analyze and OptimizeSystem PI analysisAdd more detailed models in phasesPCBPackageDieVRMDecapsDecapSoC designs have many functional blocks and millions of instances which are different in operation and requirements. With higher frequency and faster response time requirements, this puts a stringent requirement on the power supply noise budget. As the process node advances, the on-chip wires and vias get very resistive. Low power designs also mean multiple domains to be analyzed with different voltages.On top of that, system design of board and package adds complications, and have huge impact on the system resonance and noise behavior. The complicated system model may lead to stability and convergence problems for simulations.- Signoff stage is too late for changes ….- Strong interactionSince package/board designs are also concurrent with chip design, it is difficult to get an extracted netlist early in the design cycle. It is also difficult to get vectors for chip activity early in design cycle. Without the early System model, waiting on a full DvD analysis run late in design phase leaves us with very few options to fix the Power Integrity issues seen.
3Power Delivery Network Model Pkg DecapPDN is a complex network of interconnects that delivers charge from a VRM to devices on a chip.Shown here is the representative PDN system which is hierarchically modeled with different stages: VRM, PCB, PKG and the chip.This modeling will provide a system level framework for the PDN simulation. Using the model, we can simulate and observe supply waveform at the die supply pads.So, the strategy is to minimize the impact of design parameters on the PDN by:Generating the System PDN model to enable early system level analysis for Package and board designModel Package and board impedance at an early stage for dynamic voltage drop analysisBuild options for on chip, package and board decapsIn the detailed DvD analysis for signoff of the on-chip grid from the Pad to logic gates, we use the commercial DvD tools.Early System ModelSignoff ModelBoardLumped RLCFull WavePackageChipChip power modelPhysical database
4Generating chip model Estimate chip impedance Intrinsic and Intentional decapEstimate Rdie / Cdie at operating frequenciesChip impedance can be modeled as a simple R and C model.Total effective C is composed of: C(intrinsic of devices), C(decaps), C(grid) and C(load).Each of these can be estimated based on library data, die size, floorplan/power plan and number of devices. Based on the frequency of operation of each mode, the impedance will vary. It will be necessary to tune the model to each operating mode.As SoC has many non-switching gates that act as intrinsic decaps, adding intentional decap reduces the noise level, but it may not be a significant reduction.Operating freq
5Z11 Plots ComparisonBoard LCDecap Self-resonanceLpkg CdieImpedancelog-log plotBoardRSince DvD is mainly dependent on System Impedance, it is critical to analyze the frequency domain response.This plot compares 4 different simulation options with and without the board modelAnd with package including and not including the embedded decaps.Adding the board model elevates the lower frequency range inductance value.The embedded decaps lowers the whole impedance curve.As the Z11 is a function of frequency, the final noise level also depends on the frequency content of the current.If the system operation doesn’t have frequency components close to the resonance peak, system parameters do not have much impact on the noise. However if the system has activities like transition from a quiet mode to active, the system resonance could introduce huge noise.FrequencyBoard + Pkg (embedded decap) + DieBoard + Pkg (substrate only) + DieDie + Pkg (with embedded decap)Die + Pkg (Substrate only)Adding board model changes the Z11 plotsImpact on time-domain noise depends on freq content
6Understanding Current Signature Demand current = f (circuit switching activity)FFT (current)Mode 1Mode 2Energy concentrated at harmonics of 50MHzFFT up to 500MHzEnergy concentrated > 500MHzThe other component of chip power model is the current load (demand current).The frequency signature of the demand currents is important.Here are two representative FFT plots for two vectors: Mode1 and Mode2.Mode1 has more middle frequency content with distinctive peaks at 50MHz and its multiples. Mode2 has frequency contents concentrated towards the higher frequency, like more than 500MHz.As a typical PDN impedance curve has resonant frequencies in the middle range, Mode1 will induce much more noise. The design, board and package parameters make huge impact on the noise. However, Mode2 will be more immune, as the high frequency contents are already bypassed by the on-chip decaps.FFT up to 3GHz
7Optimization: Impact of PDN components Adding on-chip decapsChanging Package modelAdding embedded decapsUpdating board Model-- Board + Pkg (embed decap)-- Pkg (no decap)-- Board+ Pkg (no decap)-- Pkg (embed decap)Voltage at PadsTo start looking at the impact of different PDN components on the Power Integrity, first we look at on-chip decaps.On-chip decaps can have a big impact on the noise value. It not only moves the system resonance peak and value, but also impact the ability of bypassing the high frequency noise. The total decap amount is lumped and represented in the System PI model. However, to distribute the decaps effectively on the chip, we can use the DvD tool.As an experiment, we varied the on-chip intentional decap amount by 2x to 6x. The table shows the impact of on-chip decap citing the results from DvD tool and comparing it the System PI results (he second set of columns shown). Again, the results correlate well within 10-15% percent.Sim Time
8Impact of On-chip Decap on DvD No DecapWith DecapVCD1These plots show the specific zoomed in regions on the SoC where the On-chip decap impact can be seen.These are 2 different vectors showing a similar trend.Adding the On-chip decap helps to reduce the DvD in specific local spots as expected. In practice, the overall gain the reducing worstcase noise will be limited by how much intentional decap can be added to a design.VCD2
9On-Chip Decap & Package Core Thickness Impact Here, the impact of On-chip decap and package variations is shown in the histograms.Increasing the amount of on chip decap causes the histogram to shift towards left (less DvD)The bottom plot shows the histogram of Instance DvD with 2 different packages.Using a thicker package causes a slight constant shift in the DvD of all instances.The shift can attributed to the change in impedance of the package.
10Impact of Package and Board impedance Including Board impedance impacts DvD resultsHaving Package/ Board decaps will also impact DvDSignificant DvD impact is seen in certain modes due to board impedance. Similar DvD impact is seen with Package and Board decaps included.The Instance voltage drop waveform shows how the decaps and the board impact the voltage drop at a worst instance.Including the Board model introduces a fixed drop on top of the previously seen DvD. The decaps smoothen out the noise peaks.So its important to include board and embedded decap models also in DvD simulations.
11Summary For Power Integrity verification: Model the system early Critical to model all components of the system PDNTime-domain and Frequency domain analysisModel the system earlyEstimated and lumped models to predict the PDN responseUse the system model to study effects of different PDN parameters.In conclusion, We make a strong case for simulating a complete PDN for verifying Power Integrity. Just doing a chip level DvD analysis in isolation will not lead to accurate analysis and not help optimize the PDN. In addition to the time domain voltage drop analysis, need to do a frequency domain analysis to understand PDN response.We have seen how the System PI simulation can be used to optimize the PDN. The results from System PI simulation correlate well with a full DvD analysis done at signoff stages.References:“Package Modeling and Verification for On-Chip Power Integrity Analysis”, Li H., You E., Gill H., Samsung, User Track 49th DAC, San Francisco, June 2012.“Applying a CPM in System Power Integrity Analysis”, Brooks R., Lin J., Harisharan U., UserTrack of 46th DAC, June 2009.“Understanding Power Integrity as a System wide challenge”, Elmore M., Electronic Design, April 2012.System PI ModelCompareDetailed DVD Database