1. Combinational Logic Circuits
Digital Logic Design
Combinational Logic Circuits
Continue (Functions of CC)

2. Combinational Circuit Implementation of Decoders
Binary Adder

3. Implementing a Binary Adder Using a Decoder
S(X,Y,Z) = m (1, 2, 4, 7)
C(X,Y,Z) = m (3, 5, 6, 7)
3 inputs and 8 minterms
 Use a 3-to-8 decoder.

4. Implementing a Binary Adder Using a 3-to-8 Decoder

5. 3-6 ENCODERS
ENCODER n m
m ≤ 2n

6. 3-6 ENCODERS Inverse operation of decoder.
The output lines generate the binary code corresponding to the input value.
Assume only 1 input has the value of 1 at any given time.
Example:
Octal-to-binary encoder.

7. Truth Table for Octal-to-Binary Encoder

8. Priority Encoder

9. What about when 2 inputs are 1 at the same time?
Use “Priority Encoder”
To ensure only one input is encoded.
e.g.
D3 = D6 = 1
 Output = 110
(D6 has a higher priority than D3)

10. Priority Encoder …
If 2 or more inputs are equal to 1 at the same time, the input having the highest priority is the one encoded.
Example: 4-input Priority Encoder
V (valid) =1 when 1 or more input is equal to 1.

11. Condensed Truth Table of Priority Encoder
output => don’t care
input => product term that
is not minterm

12. Logic Diagram of a 4-Input Priority Encoder

13. Functions of Combinational Logic
Adder Encoder
Comparator Decoder
Multiplexer Demultiplexer
Parity Generator Parity Checker
Code Converters

14. ADDERS
Half Adder
Full Adder

15. Half Adder X 1 Y S C-out Half Adder Truth Table: S(X,Y) =  (1,2)
Adding two single-bit binary values, X, Y
produces a sum S bit
and a carry out C-out bit.
This operation is called half addition and the circuit to realize it is called a half adder. X 1 Y S
C-out
Half Adder Truth Table:
Inputs
Outputs
S(X,Y) =  (1,2)
S = X’Y + XY’
S = X  Y
C-out(x, y, C-in) =  (3)
C-out = XY X Y
Sum S
C-out
Circuit
Half
Adder X Y S
C-OUT
Block diagram/ Symbol/ Black- box view

16. Full Adder Full Adder Truth Table X 1 Y S C-out C-in
Sum S
C-in X 1 Y XY 2 3 6 7 4 5
Adding two single-bit binary values, X, Y with a carry input bit C-in
produces a sum bit S
and a carry out C-out bit.
Full Adder Truth Table X 1 Y S
C-out
C-in
S(X,Y, C-in) =  (1,2,4,7)
C-out(x, y, C-in) =  (3,5,6,7)
Inputs
Outputs
S = X’Y’(C-in) + X’Y(C-in)’ + XY’(C-in)’ + XY(C-in)
S = X  Y  (C-in)
C-in X 1 Y XY 2 3 6 7 4 5
Carry C-out
C-out = XY + X(C-in) + Y(C-in)

17. Full Adder Full Adder Circuit Using AND-OR: Circuit Block diagram FullXY
YC-in
C-out
XC-in X Y
C-in
X’Y’C-in
XY’C-in’
Sum S
X’YC-in’
XYC-in X’ Y’
C-in’
Circuit X X’ Y Y’
C-in
C-in’
Full
Adder X Y S
C-in
C-out
Block diagram

18. Full Adder Full Adder Circuit Using XOR: Full Adder C-out Sum S X Y S
YC-in
C-out
XC-in X Y
C-in
Sum S
Full
Adder X Y S
C-in
C-out

19. HA`and `FA symbols

20. Arrangement of 2 half-adders to form a full-adder
CASCADE

21. Exercise: Determine the output values
Σ=1, 𝐶=0
Σ=0, 𝐶=1

22. 2-Bit Parallel Adder

23. Determine the sum of this 3-bit parallel Adder

24. 4-bit Parallel Adder

25. Bigger Adders 8-bit using two 4-bit Adders 16-bit using four

26. Larger Adders
Example: 16-bit adder using 4, 4-bit adders
Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15)
producing a 16-bit Sum S (bits S0 to S15)
and a carry out C16 from most significant position.
4-bit
Adder
C-in
C-out
C0 =0 C4 C8
C12
C16
Data inputs to be added X (X0 to X15) , Y (Y0-Y15)
Sum output S (S0 to S15)
Y3Y2Y1Y0
X3X2X1X0
S3 S2 S1 S0
Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder
= 4 x 2 n x8
or gate delays

27. A 4-bit parallel ripple carry adder
-> 2*4 = 8.
Thomas L. Floyd Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

28. n-bit Carry Ripple Adders
An n-bit adder used to add two n-bit binary numbers can built by connecting in series n full adders.
Each full adder represents a bit position j (from 0 to n-1).
Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at the higher position j+1.
The output of a full adder at position j is given by:
Sj = Xj  Yj  Cj
Cj+1 = Xj . Yj + Xj . Cj + Y . Cj
In the expression of the sum Cj must be generated by the full adder at the lower position j-1.
The propagation delay in each full adder to produce the carry is equal to two gate delays = 2 
Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position , the total propagation delay of the adder is approximately:
Total Propagation delay = 2 n

29. 4-bit Ripple Carry Adder
X3X2X1X0
S3 S2 S1 S0
C-in
C-out C4
Y3Y2Y1Y0
C0 =0
Inputs to be added
Sum Output
Adds two 4-bit numbers:
X = X3 X2 X1 X0
Y = Y3 Y2 Y1 Y0
producing the sum S = S3 S2 S1 S0 ,
C-out = C4 from the most significant
position j=3
Total Propagation delay = 2 n8
or 8 gate delays
Full
Adder X1 Y1 S1
C-in
C-out X0 Y0 S0
C0 =0 X2 Y2 S2 X3 Y3 S3 C1 C2 C3 C4
Data inputs to be added
Sum output
Cascade 4 full adders to get a 4-bit full adder

30. 1’s Complement and 2’s Complement Hardware
The 2’s complement of a binary number is formed by adding 1 to the 1’s complement.
2’s complement = (1’s complement) + 1

31. How to use an adder as a Subtractor?

32. Building a Subtractor using an Adder and 2’s Complement (for positive numbers)
A – B = A + (-B) = A + B + 1
To perform subtraction using an adder, we invert B, and use Cin =1.
2’s complement
Try drawing this diagram…

33. Equality Comparator Inequality Comparator

34. Equality Comparator
To compare two binary strings (or binary words) to determine if they are exactly equal.
Truth table for a comparator:
What is the Boolean expression for this truth table?
Can you draw the circuit for basic comparator?
A B A=B
0 0 1
0 1 0
1 0 0
1 1 1

35. Equality Comparator
Comparing two binary strings (or binary words) to determine if they are exactly equal.
Truth table for a comparator:
1-bit comparator
A B A=B
0 0 1
0 1 0
1 0 0
1 1 1
A=B is same as output for Ex-NOR gate

36. Basic Equality Comparator Operation

37. Basic Comparator Operation

38. 1-bit Comparator with Inequality outputs
To compare 2 binary numbers, each 1-bit wide.
The result of the comparison are single bit outputs that indicate whether the numbers are equal to each other, or if one number is greater than or less than another.
A=B?
A<B?
A>B?

39. 4-bit Comparator with Inequality Indication

40. Multiplexers & Demultiplexers
MUX & DEMUX

41. Mutiplexer (MUX)
A circuit that selects binary information from one of many input lines, and directs the information to a single output line.
The selection of a particular input line is controlled by a set of input variables, called “selection inputs”.
Normally, there are 2n input lines and n selection inputs.
Output lines = ?

42. 2-to-1 Multiplexer Data selector
A 2 input multiplexer
Data selector
SELECT input code determines which input is transmitted to output Z.

43. 4-to-1 Multiplexer Write the output equation for Z Verify the circuit
A 4 input multiplexer
Write the output
equation for Z
Verify the circuit
above
Z = I0 S1’ S0’ + I1 S1’ S0 + I2 S1 S0’ + I3 S1 S0

44. 8-to-1 Multiplexer
Larger multiplexers can be constructed from smaller ones.
An 8-to-1 multiplexer can be constructed by cascading smaller multiplexers as shown:

45. Demutiplexer (DeMUX) Opposite function of the multiplexer.
Information received from a single line is transmitted to one of 2n possible output lines.
The output line chosen is controlled by the n selection inputs.
Black box view?

46. 1-line-to-8-line multiplexer
Demultiplexer
Data input is transmitted to only one of the outputs as determined by the select input code.

47. 1-to-2 DeMUX D 1 Y1 Y0 Select Black box view Output equationsD 1 Y1 Y0
Select
Black box view
Output equations
Logic circuit
Z = SD + S’D
Y0 = SD
Y1 = S’D

48. 1-to-4 DeMUX

49. Mux-Demux Application: Example
This enables sharing a single communication line among a number of devices.
At any time, only one source and one destination can use the communication line.

50. Parity Generator & Parity Checker
Odd Parity
Even Parity

51. Error-Detection
A parity bit is a scheme for detecting errors during transmission of binary info.
A parity bit is an extra bit included with the binary message to make the number of 1’s either odd or even.
The message, including the parity bit, is transmitted and then checked at the receiving end for errors.
An error is detected if the checked parity does not correspond to the one transmitted.

52. Error-Detection
The circuit that generates the parity bit in the transmitter is a parity generator.
The circuit that checks the parity bit in the receiver is a parity checker.

53. Error-Detection Parity generator truth table
*For odd parity, the bit P is generated so as to make the number of 1’s odd (including P)
X Y Z P
Odd Parity Generator

54. *The three-bit message (X, Y, Z) and parity bit (P) are transmitted to their destination, where they are applied to a parity checker circuit. An error occurs during transmission if the parity of the four bits is even, since the binary info transmitted was originally odd. The output C of the parity checker should be a 1 when an error occurs, i.e. when the number of 1’s in the four inputs is even.
X Y Z P C
Odd Parity Checker

55. Parity is used in digital circuits to check for errors in transmission.
In Four bit transmission a parity bit is added to make the fifth bit.
In a eight bit transmission a parity bit is added to made a ninth bit.
And so on.

56. ODD Parity
In ODD parity when we add the bits together disregarding weight we get or want to get an odd number.
is a four bit message add a parity bit to make it odd
Odd parity is satisfied
is an eight bit message add a parity bit to make it odd
Odd parity is satisfied
Parity bit
Disregarding = Ignoring

57. EVEN parity
In EVEN parity when we add the bits together disregarding weight we get or want to get an even number.
is a four bit message add a parity bit to make it even
Even parity is satisfied
is an eight bit message add a parity bit to make it even
Even parity is satisfied
Parity bit

58. How to generate a parity bit
Use exclusive ORs and Exclusive NORs

59. How to make a parity checker

60. Odd or even parity
~ 0 out of a parity checker means the parity checks and all is ok
~ 1 out of a parity checker means there is an error

61. This Summary is an Online Content from this Book: Morris Mano, DIGITAL DESIGN, 4th Edition, Prentice Hall, 2007
It is edited for Logic Analysis and Design Course by: T.Mariah Sami Khayat Teacher Adam University College For Contacting:
Kingdom of Saudi Arabia
Ministry of Education
Umm AlQura University
Adam University College
Computer Science Department
المملكة العربية السعودية
وزارة التعليم
جامعة أم القرى
الكلية الجامعية أضم
قسم الحاسب الآلي