1. 1 Back-Of-Crate : BOC Status Oct, 2002 BOC is the optical fibre interface for the ROD Receives module control data from ROD, performs clock-data encoding, sends down fibres Receives module data on fibres, and formats data for the ROD input Provides individual data delays and other timing functions Houses the S-Link interface Overview BOC prototype, (BOC-0 ): BOC-0 was the proof-of-principle board Testing showed: Communication with ROD works fine TX: Clock and Command stream OK RX: Data Stream OK Eye pattern good Timing measurement procedure OK De-muxing of PIXELS 80 MS/s data demonstrated

2. 2 BOC1: BOC1 is the pre-production prototype: Uses production compatible components Should move seamlessly into production Changes from BOC0: A (remarkably small) number of PCB fixes Reduce PCB depth to 220 mm (was 240 mm) Add Power Monitor and Power-up Reset Major Revision of Clock Circuits: PLL with fail-safe provisions Increase range of fine clock delay to 10ns in 10ps steps All PECL & LVDS implementation (other then delay chips) Should give reduced short-term jitter and guaranteed mark-space All RX streams to have Pixel data de-muxing ability Move to New OptoElectronics and ASICs: see later slide Back-Of-Crate : BOC Status Oct, 2002

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4. 4 BOC1 Data RX Section Clock S-Link Clock & Command

5. 5 New Opto and ASICs VCSEL12 and PIN12 arrays by Academica Sinica of Taiwan: BPM12 Clock/Data Encoder/Driver - MAJOR rework of BPM4: 12 streams rather than 4 Drives common cathode lasers Many other improvements DRX12 Receiver already a proven component New Opto Plug-In Modules by Academica Sinica: Optical Transmitter Plug-In “OptoTX”: BPM12 + VCSEL12 + DACs for I Control 12 streams per module 4 modules per BOC - providing 48 fibre drivers per BOC Optical Receiver Plug-In “OptoRX” : DRX12 + PIN12 + Threshold DACs 12 streams per module 8 modules per BOC - providing 96 fibre receivers per BOC New versions with Samtec connector being designed - more rugged, easier to assemble and use Back-Of-Crate : BOC Status Oct, 2002

6. 6 BOC1 Status: PCB manufactured (11 off) Parts delivered (for 11 BOCs) (excluding optical modules) First board assembled and extensively tested 3 more assembled, ready for test (Cambridge, LBL & Oxford) Received 5 TX & 4 RX Opto Plug-Ins 10 TX & 10 RX Opto Plug-Ins with new connector awaited Fabrication limited by lack of optical modules Testing: The optical clock and command path functioning OK The optical received data path functioning OK The pixel specific part of the BOC1 yet to be tested. Combined tests of ROD-with-BOC0 driving single SCT detector module well advanced ROD-with-BOC1 work about to be started at Cambridge & LBL Back-Of-Crate : BOC Status Oct, 2002

7. 7 Delay Chip Circuit Changes BOC uses 26 PHOS4 Quad Programmable Delay chips (designed by CERN Micro-Electronics Group) for Data alignment and for Clock Generation. These work very well, and are indispensable. But under some circumstances the chips’ delay-locked-loop can get in an anomalous state, yielding around twice the expected delays. A method of forcing them out of this state has been found. A number of simple BOC design changes are planned: Added circuitry to allow the delivered delays to be measured Clock circuitry change to provide the “Remedial Action” on demand Control circuitry change to implement the dummy I2C Reset recommended in the PHOS4 data sheet shortly after power-up Back-Of-Crate : BOC Status Oct, 2002

8. 8 Immediate Schedule: A number of circuit changes - mostly very minor - are planned; none invalidate the use of the existing BOC1 for Atlas development and commissioning work The 11 BOC1 cards will be populated as required, and are expected to meet Atlas needs until Spring 2003 Small numbers (~20) of Opto Plug-Ins will suffice until late ‘02 A converter card will be made to use the new, connectorized Opto Plug_Ins on the current 11 BOC1 cards. Back-Of-Crate : BOC Status Oct, 2002 Moving to the Production Version: The Artwork will be upgraded as soon as the fibre retention and laser safety interlock details have been decided. Other changes will probably arise from the User Evaluation. New PCBs manufactured after User Evaluation and Review Plans