Cluster Processor Module : Status, test progress and plan Joint Meeting, Mainz, March 2003.
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Cluster Processor Module : Status, test progress and plan Joint Meeting, Mainz, March 2003
Cluster Processor Module: plan Real Time Data Path: –SRL Chip to CP chip –Lvds Rx to SRL chip Latency measurement 2nd CPM to be tested Subsystem Test Lvds Source Module
Real Time Data Path Test: Choice of the CP chip F/W Real Time Data path was tested via the “ScanPath” F/W, which record 160 MHz data at the input of the 108 input of the CP chip Previous test shown that always couple of data are corrupted The F/W used was selected among 4 phases the best one for all inputs But the present device used (XCV1000E upgrade 6) has not enough resources to give a stable calibration for all channels F/W changed for 2 phases, a bit better but still not enough Decide to go for one phase: –All onboard data strobe by the same phase –All BP data strobe by the same phase, but delay by 1.5 ns to the phase for the onboard data
From 4 phases to 1 phase 4 phases2 phases1 phase Pin #1 Pin #2 Pin #3 Pin #4 160 MHz data stream….
Real Time Data Path Test: Choice of the CP chip F/W for the slice test The one phase works very well -> see Christian talks One phase F/W will be used for the Slice Test Extra boards will be assembled with same device as the CPM#1 Future: Fastest and bigger FPGA,VirtexII, will be used for CPM, where the 4 phases method could be implemented
80 serialisers locked Perform timing scan by changing clock on Serialiser Stable over ~20 ns Only one serialiser shows some problem: –One pin of one Lvds Rx not soldered: strobing on opposite edge of other receivers More details in Christian Talk Bit Error Rate Tester to be implemented to perform overnight run (see Tamsin Moye talk) Real Time Data Path:LVDS data to Serialiser
Latency Measurement Can save a couple of ns if you strobe near the beginning of the pulse at the input of the serialiser Results to be double checked with simulation for the CP and Serialiser Ian claims it can save 18 ns, present design not thought enough Latency expected was of 9 ticks (TDR)
2 nd CPM appears … A second CPM has been assembled JTAG shows that 4 CP chips are not correctly connected Assembling company blamed the board was not clean, as been stored for too long (1 year!) Produce new PCBs before assembly of new boards Test to be done with present 2 nd CPM
Subsystem Test With 2 CPMs working, we can tested –Backplane links –Nearly full CP algorithm With one CPM and 5 DSS populated with LVDS DB –Fully drive LVDS input of CPM –Test noise and Xtalk With one CPM and one ROD –Test G-link output –Test L1A handling in CPM With one CMM –Test backplane link
Subsystem Test Schedule at B’ham systemH/W NeededStatusWhenS/W Needed CPM to CPM One CPMavailablenowComplete CPM services LVDS to CPM 5 Dss 5 TTCdec Optical FanOut Under test Available @ CERN monthHandling 2 CPUs (netBus?) CPM to ROD 1 RODtestedweeksnone CPM to CMM 1 CMM 1 Gio Card Under test monthComplete CMM services
CPM Tests Integrated with Run Controller –Loading of F/Ws from database –Setting thresholds, mask –…(discover everyday) RC can deal with all previous test modes Still some work to be done for CPM services:
Lvds Source Module Present source of Lvds signals come from DSSs. Lot of DSSs required to fully populated one board Limited number of DSS available Decide to design a board dedicated to generated up to 44 or 88 LVDS signals –Use for production testing –Simple design, might be ready quickly and use for testing Design to be talk with Richard