1. EEL 5722 FPGA Design Fall 2003 Digit-Serial DSP Functions Part I

2. Digit-Serial Arithmetic Bit-serial arithmetic architectures process one bit at a time and are suitable for low-speed applications. Bit-parallel arithmetic architectures process one whole word of the input sample in one clock cycle and are ideal for high-speed applications, but they require a great deal of hardware. To avoid the disadvantages of the bit-serial and bit-parallel computation, the concept of digit-serial implementations has been proposed. In DSP applications, it is desirable to combine the area efficiency of a bit-serial architecture with the time efficiency of a corresponding bit-parallel architecture into a single area-efficient and time-efficient digit-serial architecture.

3. Digit-Serial Arithmetic In a digit-serial arithmetic implementation, the W-bits of a data word are processed in units of the digit-size N in W/N clock cycles. This leads to arithmetic operators that have smaller area than equivalent bit-parallel arithmetic designs and have a larger throughput than equivalent bit-serial arithmetic designs. By considering a range of values for the digit-size, one can search the design space to find the optimum implementation for a given application.

4. FPGA Implementations Various DSP functions are implemented on XC4000 FPGAs. The design methodology consists of:  Manual design of the architecture of a DSP function.  Schematic capture using the macro library of XC4000.  Placement and routing of the design. Larger digit-serial DSP functions are assembled by performing an automatic place and route of the digit-serial arithmetic macro blocks.

5. XC4000 FPGA

6. XC4000 Carry Paths

7. XC4000 Carry Logic

8. XC4000 Carry Resources

9. Use of XC4000 Carry Logic

10. Performance Evaluation Comparisons use three metrics: area, time, and area x time, where time refers to the data sampling period (for complete words) or the inverse of the throughput. Timing simulation results are obtained from the post-routing annotations of the design by Xilinx Design Manager. The following parameters are used to estimate the area/delay:  T LUT ─ combinational delay (2.7 ns)  T FF ─ flip-flop delay (clock-to-output = 3.0 ns)  T Fast ─ fast-carry logic delay (Bypass carry logic delay = 0.6 ns)  T IR ─ delay incurred in the routing between each CLB (3.0 ns)  W ─ word length  N ─ digit size

11. Digit-Serial Arithmetic Blocks The basic functions for DSP applications include addition, negation, and storage registers used for delay. These basic functions can be assembled to construct complex structures such as accumulators and multipliers. With a digit-serial DSP architecture, these hardware units can be parameterized by the digit size.

12. Digit-Serial Adder A digit-serial adder is a circuit that adds two digits along with a previous carry bit and produces the same digit and a new carry bit. The two operands, A and B, are fed one digit at a time into the adder. The carry-out (CO) from the digit-serial adder is fed back into the first full adder during the next clock cycle, when the next digits of the input have arrived. A digit-serial adder with N = 1 corresponds to the bit-serial adder.

13. Digit-Serial Adder In XC4000, a bit-serial adder requires 1 CLB to generate the sum and load the carry into the FF. The number of CLBs required are the number of bits in the word. A digit-serial adder with N = 2 uses all three LUTs, three of the FFs and one fast-carry logic unit.

14. Digit-Serial Subtractor To do subtraction, the B input is complemented and a logic 1 is fed into the initial carry in. A digit-serial subtractor implemented on XC4000 FPGA has:

15. Digit-Serial Adder/Subtractor When the Add input is high, two digits are added with a carry-in, producing a digit sum (S3 – S0) and CO in the N = 4 digit-serial adder/subtractor. When the Add input is low, (B3 – B0) is subtracted from (A3 – A0), producing a digit difference (Out3 – Out0) and CO. The fast-carry logic unit is independent of the LUTs, but it shares some of the same inputs with the LUTs.

16. Bit-Level Pipelined Digit-Serial Adder The previous digit-serial adder has a feedback loop of the carry bit into the first full adder, and cannot be pipelined at the bit level. The critical path in the conventional N = 4 digit-serial adder is four full-adder delays. As such, the critical path increases with digit size.

17. Bit-Level Pipelined Digit-Serial Adder The bit-level pipelined digit-serial adder can be implemented by using two carry propagate adders (CPAs), where the carry bit produced by the first CPA is propagated forward and added to the next digit output using the second CPA.

18. Bit-Level Pipelined Digit-Serial Adder When the current output of the first CPA is 2 N -1, the carry bit obtained from the second CPA is equal to 1 and the carry from the previous digit is 1. In this case, the carry to the next significant digit should be set to 1. The digit from the CPA is fed into an N-input AND gate to check whether it is equal to 2 N -1. This is performed by using an array of AND gates arranged in a tree structure.

19. Bit-Level Pipelined Digit-Serial Adder The resulting bit and the carry bit obtained in the previous cycle are fed to a two-input AND gate to check whether the current output of the first CPA is 2 N -1 and the carry from the previous digit is 1 simultaneously. The output bit and the carry of the current digit are fed to a two- input OR gate to calculate the correct carry bit to be fed to the second CPA. The adder can be pipelined in four levels, and hence the critical delay can be reduced to (3 Half- adder + XOR delay).

20. Bit-Level Pipelined Digit-Serial Subtractor A similar approach can be used to pipeline a digit-serial subtractor. The area and delay of a N = 4 pipelined adder/subtractor is: Area = 6.5, Delay = 2T LUT + T FF + T IR.