1. ESD Evaluation of the Emerging MuGFET Technology
C. Russ et. al 2005 ESD/EOS Conference

2. Oh No! Is ESD Going to be MuGGed by Yet Another Technology Development??
Give me your ESD!
Dr. MuGFET

3. Purpose of this work
Introduce the exciting new Multi-Gate Advanced Transistor Technology called the “MuGFET” and assess its sensitivity to high current ESD behavior
Investigate suitable ESD protection methods for this new technology

4. Outline Introduction: MultiGate FETs (MuGFETs) ESD Characterization
Fully depleted (FD) MuGFETs
Partially depleted (PD) planar FETs
Diodes
Failure analysis
Protection approaches
Conclusions

5. Introduction (1) Classical FET in Bulk Si G L W D S
SiO 2 Si
Gate G L W D S
current
current
Scaling expected to become difficult due to Short Channel Effects (32nm node and beyond)

6. Introduction (2) Planar FET Device in SOI G L W D S
SiO 2 Si
Gate G L W D S
current
current
Low junction capacitance  speed!
Good body control in fully depleted SOI
Requires costly wafers with ultra-thin Si-film 

7. Introduction (3) MuGFET Device (or “Fin”-FET) W G L D S
2 sides: double-gate
3 sides+top: tri-gate
current W G
SiO 2 Si
Gate L D S
current
Channel enclosed by multiple (2, 3, 4) gates  Best body control (fully depleted)  Suppression of Short Channel Effect
Best candidate for continued technology scaling

8. Introduction (4) Fin height: 60-88nm (present), 30-40nm (target)
depleted
Fully
Fin height: 60-88nm (present), 30-40nm (target)
Fin width: 50nm (present), 20-30nm (target)
Capability to carry ESD current?

9. Outline Introduction: MultiGate FETs (MuGFETs) ESD Characterization
Fully depleted (FD) MuGFETs
Partially depleted (PD) planar FETs
Diodes
Failure analysis
Protection approaches
Conclusions

10. MuGFET fully depleted (FD) Planar SOI partially depleted (PD)
Test structures
Wgeo
SOURCE
GATE
Wfin =
50nm
200 nm Lg aS
pitch L
DRAIN N+
MuGFET fully depleted (FD) aD
SCGS Lg
MDR
Wgeo L
GATE
SOURCE
DRAIN N+
Planar SOI partially depleted (PD)

11. Test structures NMOS Gated diode S D n+ G G A C p+ n+
Nickel
Silicide
NMOS
Gated diode G A C p+ n+
Buried oxide
Buried oxide
NMOS and Gate diodes available as MuGFET (‘Fin’) and planar SOI types
Fin width = 50nm, Fin heights = 88 and 60nm
Nickel silicided (no silicide blocking)

12. MuGFET: Grounded Gate NMOS
Unprecedented high ESD sensitivity  failure instantaneous after breakdown!
L pushes out breakdown, but no snapback visible

13. MuGFET: MOS-diode, Gate tied high
Gate biasing allows moderate MOS current flow
Damage occurs as soon as Vbd of GGNMOS-case is reached  non-uniform current flow?

14. Planar PD SOI NFET: Grounded Gate
More robust (~2mA/um), reproducible and scalable
Very steep on-characteristics
L pushes out BD, minor snapback occurs

15. Gated Diodes: Fins + Planar (fwd. mode)
It2 [mA/um]
film thickness tsi
88nm
60nm
Fin-type
500 fins
Wsi=25um
16.8
15.2
Planar
W=50um
11.6
9.6
Excellent ESD performance (Fin-type and planar)!
Fin-type diodes show less sensitivity to tsi

16. Gated Diodes: Fins + Planar (rev. mode)
Breakdown voltage much higher than for any FET
Fin-type diodes in BD do not show premature failure as seen in NFETs  resistive ballasting

17. Outline Introduction: MultiGate FETs (MuGFETs) ESD Characterization
Fully depleted (FD) MuGFETs
Partially depleted (PD) planar FETs
Diodes
Failure analysis
Protection approaches
Conclusions

18. Failure Analysis: NFETs
Planar
PD SOI D
80nm
ESD S G
metal
MuGFET
No damage
MuGFET: localized damage of neighboring fins
extremely low ESD performance
Planar device: uniform damage along gate width
reasonable ESD performance

19. Failure Analysis: Diodes (fwd. mode)
MuGFET
Planar
MuGFET diode: uniform damage of fins
high ESD performance
intrinsic current capability of technology reached
Planar diode: no failure in silicon (contact failure?)

20. Failure Analysis: Pulse Width vs. It2
It2 [mA]
Tpulse
100ns
500ns
2500ns
Planar NMOS W=50um
75-80
60-69
49-57
FinFET diode 500 fins, Wsi=25um
380
290
230
Planar diode W=50um
480
335
235
‘Wunsch-Bell’-unlike characteristics obtained
Planar MOS and FinFET diode:
smaller sensitivity due to more heat sinking

21. Protection Approaches
pad
PD planar
ESD clamp
FD MuGFET
driver
Input protection: dual diode + power clamp approach
Output drivers: PD planar device as local clamp provides solution integrated into process
Provides both performance and ESD protection

22. Conclusions New issues for emerging Multigate technologies:
FinFET MOS: extremely ESD-susceptible
Local burn-out of fins
Planar MOS: reasonable ESD hardness
Uniform failure signature (even fully silicided!)
Available in same process
Lower trigger than FinFET  local clamp
Gate-biased MOS:
Possible as protection, BJT conduction must strictly be avoided
Gated diodes (Fin-type and planar):
Diodes needed in any protection scheme
FinFET diodes: high ESD currents possible!

23. T. Pompl et. al IRPS Conference Infineon Technologies
Gate Dielectric Integrity along the Road Map of CMOS Scaling including Multi-Gate FET, TiN Metal Gate, and HfSiON High-k Gate Dielectric
T. Pompl et. al IRPS Conference
Infineon Technologies
Texas Instruments

24. Purpose
Investigate:
Influences of multi-gate architecture and metal gate on gate dielectric reliability.
Demonstrate:
Dielectric reliability trend along the road map towards a CMOS process using triple gate architecture, metal gate, and HfSiON gate dielectric.

25. TEM Cross Sections of Vertical Silicon Fin
fully-depleted triple gate FET with poly-Si
gate and SiO2
(ISSG: 20 Å)
fully-depleted triple gate FET with TiN/poly-Si gate and SiO2
(ISSG: 17 Å)
fully-depleted
triple gate FET
with TiN/poly-Si gate and HfSiON
(ALD & post anneal in NH3, EOT: 10.5 Å, 20% Si, 7-8% N, bottom SiO2: 8 Å)

26. High Volume TDDB checks for Weak Spots
The total length of tested top fin edge is 1.5 m per distribution.
State of the art gate dielectric reliability can be achieved for CMOS processes using vertical multi-gate architectures.

27. Influence of Crystal Orientation
Orientation of the silicon fin on {100} substrate:
SiO2 grown on silicon side walls with different crystal orientations.
No major influence on time to breakdown.
Important also for SiO2 channel interface layer of high-k stacks.

28. NFET: Time To Breakdown vs. Gate Voltage
Expectations from thickness scaling of poly-Si/SiO2 towards
using 6.5 dec. in time per nm.
17 Å
10.5 Å
SiO2 & TiN: NFET meets standard reliability performance.
HfSiON & TiN: NFET becomes more critical at stress level.

29. PFET: Time To Breakdown vs. Gate Voltage
Expectations from thickness scaling of poly-Si/SiO2 towards
using 6.5 dec. in time per nm.
17 Å
10.5 Å
SiO2 & TiN: PFET becomes more critical at stress level.
HfSiON & TiN: PFET meets standard reliability performance.

30. Gate Leakage Current vs. Gate Voltage in Inversion Biasing Mode
1: SiO2 & poly-Si
2: SiO2 & TiN
PFET becomes equal to NFET
3: HfSiON & TiN
NFET gate leakage strongly increased compared to PFET.
Due to asymmetry of the high-k stack.
NFET: strong dependence of gate leakage on gate voltage needs to be considered for gate dielectric reliability.

31. Conclusions
State of the art gate dielectric reliability can be achieved for CMOS processes using vertical multi-gate architectures.
GOX reliability trend along the road map of CMOS scaling will be dominated by metal gates and high-k dielectrics.
The use of metal gate increases gate leakage current density and reduces SiO2 reliability margin for PFET devices compared to poly-Si/SiO2.
NFET & HfSiON: the extrapolation of dielectric reliability to use conditions needs to consider the strong dependence of gate leakage on gate voltage.
PFET & HfSiON: the dielectric reliability meets the level of a standard poly-Si/SiO2 gate stack of same EOT.