1. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 1 Effects of Switched-Bias Annealing on Charge Trapping in HfO 2 high-  Gate Dielectrics X. J. Zhou, a D. M. Fleetwood, a L. Tsetseris, b R. D. Schrimpf, a S. T. Pantelides b a Department of Electrical Engineering and Computer Science, Vanderbilt University b Department of Physics and Astronomy, Vanderbilt University Supported in part by Air Force Office of Scientific Research through the MURI program and the US Navy

2. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 2 Outline  Motivation  Experimental results  Switched bias annealing after X-ray radiation  Switched bias annealing after Constant Voltage Stress (CVS)  Model of device response based on  Metastable electron traps near interface (  V ot )  Primarily after radiation exposure  Proton transport & reaction (  V it )  After irradiation or CVS  Additional defect growth during longer anneal cycles

3. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 3 General Motivation  High-  dielectrics are promising candidates for future commercial and space electronics.  At last year’s IEEE NSREC, we reported more degradation (very large threshold voltage shifts) when irradiation and bias temperature stressing (BTS) were combined than when the two separate effects were assessed independently and added.  Charge trapping properties of high-  dielectrics are not well understood – more insight is needed in advance of their potential use in manufacturing.

4. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 4 Specific Motivation (from last year’s NSREC) Worst case for Circuit response: pMOS devices irradiated “off” and annealed “on Zhou, Fleetwood, Felix, Gusev, and D’Emic, TNS, 52 (6),2231, 2005 Doses: 1 Mrad(SiO 2 ); 0, ±2 MV/cm BTS: 10 min; ±2 MV/cm; 75ºC

5. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 5 Experimental details Devices Al/SiO x N y +HfO 2 /p-Si MOS caps EOT = 2.1 nm Irradiation or constant voltage stress (CVS) Rad: 10-keV X-rays; ~ 500 rad(SiO 2 )/s to 1 Mrad(SiO 2 ); E ox = 2MV/cm CVS: E ox = – 3.6 MV/cm; t = 1200s; T=25ºC Switched-Bias annealing 25ºC to 150ºC E ox = ± 2 MV/cm alternating Typical anneal time: 10 min Si Oxynitride (1.0 nm) HfO 2 (6.8 nm) Al ∆V ot and ∆V it (flatband to midgap) estimated by midgap method of Winokur et al., IEEE TNS 31, 1453 (1984)

6. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 6 Reversibility observed in ∆V ot after irradiation, during switched-bias anneals at 50ºC    V ot  increases during NBTS and decreases during PBTS  Metastably trapped electrons near interface contribute to reversibility of  V ot Rad: 1 Mrad (SiO 2 ); 2 MV/cm Anneals: ±2 MV/cm, 50  C

7. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 7 Si Al HfO 2 (6.8 nm) SiO x N y (1.0 nm) -V +V + ++ + __ ++ __ ++++____ Dominant Mechanism: ∆V ot Electrons move out of oxide during NBTS Electrons pulled back into oxide during PBTS

8. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 8  V ot reversibility increases with annealing temperature Pure electron tunneling should not depend strongly on temperature Other mechanisms must be contributing (e.g., H + motion), as we now show Rad: 1 Mrad (SiO 2 ); 2 MV/cm Anneals: ±2 MV/cm

9. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 9 Similar reversibility also observed for  V it  V it increases during NBTS, and decreases during PBTS Process not due to normal two-stage  V it buildup due to H + release in oxide More consistent with  V it buildup seen in NBTI experiments Rad: 1 Mrad (SiO 2 ); 2 MV/cm Anneals: ±2 MV/cm

10. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 10 Candidate Mechanism (Oversimplified) [structural reconfiguration likely also occurs; not just H + motion] Si Al HfO 2 (6.8 nm) SiO x N y (1.0 nm) -V +V H+H+ H+H+ Si Protons depassivate Si-H bond:  V it ↑,  V ot ↑ Protons passivate Si-H bond:  V it ↓,  V ot ↓

11. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 11  V it increases with increasing anneal temperature More than simple reversibility in charge motion after rad Additional defect growth must occur in these devices during the anneal – why? Rad: 1 Mrad (SiO 2 ); 2 MV/cm Anneals: ±2 MV/cm

12. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 12 After rad, |ΔV ot | > |ΔV it |  Both electron exchange and H + motion occur  Enhanced reversibility in  V ot consistent with large e-h (dipole) generation during rad Rad: 1 Mrad (SiO 2 ); 2 MV/cm Anneals: ±2 MV/cm @ 50  C

13. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 13 Post-CVS annealing at 50  C |ΔV ot | < |ΔV it |  Similar trend as post- rad, but now  V it dominates  No electron-hole pair creation due to low voltage; lack of radiation  Proton interactions relatively more important than for post-rad case CVS: (– 3.6 MV/cm; 1200s; 25ºC) Anneals: ±2 MV/cm

14. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 14 More annealing cycles lead to enhanced defect growth  Degradation increases with time (not just reversibility)  Defect growth increases with annealing time and temperature CVS: (– 3.6 MV/cm; 1200s; 25ºC) Anneals: ±2 MV/cm

15. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 15 Defect growth with time: post-CVS (similar trends post-rad) Low electric fields, but high enough to increase gate current Gate current increases with temperature Additional CVS stress occurs during annealing cycles at high-T Enhanced H + motion and interactions lead to increasing ∆V it, ∆V ot CVS: (– 3.6 MV/cm; 1200s; 25ºC) Anneals: ±2 MV/cm

16. June 13, 2006 2006 MURI Annual Review X. J. Zhou, et al 16 Conclusions and Implications High-κdevices can trap large numbers of compensating electrons and holes during irradiation. Leads to significant reversibility in ∆V ot during switched-bias annealing. Effects large enough to cause pMOS transistors to fail in circuit applications. Constant-voltage stress experiments show the importance of hydrogen motion and reactions on device response. Reversible with bias. But generally increasing with time and temperature. Unless effects are addressed via process improvements, qualification of high-κdevices for space application will require additional screening and testing margins, as compared to SiO 2