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MAXIM 2012 August 31 H. J. Barnaby School of Electrical, Computer, and Energy Engineering Ira A. Fulton Schools of Engineering Arizona State University,

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Presentation on theme: "MAXIM 2012 August 31 H. J. Barnaby School of Electrical, Computer, and Energy Engineering Ira A. Fulton Schools of Engineering Arizona State University,"— Presentation transcript:

1 MAXIM 2012 August 31 H. J. Barnaby School of Electrical, Computer, and Energy Engineering Ira A. Fulton Schools of Engineering Arizona State University, Tempe, AZ Total Dose Effects and Modeling Approaches for Devices and ICS

2 2012 MAXIM 2  Degradation in integrated circuits due to ionizing radiation exposure can deteriorate the circuit characteristics, potentially leading to system failure Degradation in integrated circuits due to ionizing radiation exposure can deteriorate the circuit characteristics, potentially leading to system failure  Most space electronics, implantable medical devices, and radiation/accelerator facility instrumentation therefore require hardness to total ionizing dose (TID) Most space electronics, implantable medical devices, and radiation/accelerator facility instrumentation therefore require hardness to total ionizing dose (TID) The Total Ionizing Dose Problem

3 2012 MAXIM 3 Outline  Ionizing Radiation Environment and Damage Processes  Total Ionizing Dose Effects in CMOS  Effects in Bulk CMOS  Effects in SOI CMOS  Total Ionizing Dose Effects in Bipolar Technologies  Effects in Bipolar Junction Transistors  Enhanced Low Dose Rate Sensitivity (ELDRS)  Modeling Approaches

4 2012 MAXIM 4 Outline  Ionizing Radiation Environment and Damage Processes  Total Ionizing Dose Effects in CMOS  Effects in Bulk CMOS  Effects in SOI CMOS  Total Ionizing Dose Effects in Bipolar Technologies  Effects in Bipolar Junction Transistors  Enhanced Low Dose Rate Sensitivity (ELDRS)  Modeling Approaches

5 2012 MAXIM 5 Electronic Stopping Power (after Paillet et al., IEEE TNS 2002) Electronic Stopping or Linear Energy Transfer (LET) measures energy deposited into a material by ionizing radiation LET is a strong function of energy and radiation source Total ionizing dose is a measure of energy deposited through ionization A unit of TID is a rad or a gray (100 rad = 1 gray)

6 2012 MAXIM 6 Converting Fluence to Rad(SiO 2 ) Rad (SiO 2 ) =  X  p X LET Units of Rad (Si) = (radg/MeV)(cm -2 )(MeVcm 2 /g)  = (10 6 ev/MeV)(1.6x10 -12 erg/eV)(1radg/100erg) = 1.6x10 -8 radg/MeV Example: 100MeV protons in SiO 2 - The LET for a 100 MeV protons in SiO 2 is 6.13 MeVcm 2 /g (from SRIM code) - To get total dose [rad(SiO 2 )] from a 100 MeV proton fluence (  p ), multiply  p by (6.13)x(1.6x10 -8 ) Ans. If the total fluence of 100 MeV protons for the mission is 10 12 protons/cm 2, the part will receive ~ 100 krad(SiO 2 ) from these particles Note: to compute the dose across the full proton energy spectrum, we must take into account all LETs as well as the energy attenuation of lower energy particles

7 2012 MAXIM 7 Overview of Total Ionizing Dose Damage Processes in SiO 2 (after McLean and Oldham, HDL-TR-2129 1987) Processes EHP Generation EHP Recombination Hole and H+ transport Defect formation: –Fixed oxide-trapped- charge (N ot ) –Interface traps (N it )

8 2012 MAXIM 8 EHP Generation Number of electron-hole pairs (ehp) generated in SiO 2 is computed as follows: [MeVcm 2 /g][cm -2 ] [#ehps/MeV] [g/cm 3 ] fluence SiO 2 density E p for SiO 2 is 17 eV/ehp (after McLean and Oldham, HDL-TR-2129 1987) (after Srour, DNA-TR-82-20 August 1982) EvEv ECEC + - E g ~ 9 eV EpEp ionizing radiation

9 2012 MAXIM 9 EHP Recombination (after Schwank, NSREC SC 1994) Fraction of holes surviving prompt recombination (f y ) is a function of type and energy of radiation as well as electric field. 9

10 2012 MAXIM 10 Hole Trapping Processes + + - surviving hole (p) - hole trap (N T ) - trapped hole (N ot ) fpfp - hole flux area = 

11 2012 MAXIM 11 PDE model for N ot (with simplifying assumptions) (After Rashkeev et al. TNS 2002) (steady state) (f p > 0 for all x) f ot D (No saturation or annealing and traps at interface)

12 2012 MAXIM 12 Simple closed form model for  N ot (after Fleetwood et al. TNS 1994) Model Parameters D - total dose [rad] k g - 8.1 x 10 12 [ehp/radcm 3 ] f y - field dependent hole yield [hole/ehp] f ot - trapping efficiency [trapped hole/hole] t ox - oxide thickness [cm] ε- local electric field [V/cm]

13 2012 MAXIM 13 Interface trap buildup processes - protons - Si-H (N SiH ) - dangling bond (N it ) area =  it H H+ fHfH - proton flux - hydrogen defect (N DH )

14 2012 MAXIM 14 (after Rashkeev et al. TNS 2002) f it D (f H > 0 for all x) (steady state) (assumes no saturation or annealing and traps at interface) f DH PDE model for N it (with simplifying assumptions)

15 2012 MAXIM 15 Simple closed form model for  N it (after Rashkeev et al. TNS 2002) Model Parameters D - total dose [rad] k g - 8.1 x 10 12 [ehp/radcm 3 ] f y - field dependent hole yield [hole/ehp] f DH - hole, D’H reaction efficiency [H + /hole] f it - H +, SiH de-passivation efficiency [interface trap/H + ] t ox - oxide thickness [cm]

16 2012 MAXIM 16 Empty D centers H H H H H 2 molecules Molecular hydrogen reacts with empty D centers to generate more DH centers H H DH centers H H H H 2 transport into material Rad-induced holes Impact of molecular hydrogen

17 2012 MAXIM 17 1D model fit to data (after Chen et al. TNS 2007)  N it [cm -2 ] H 2 [cm -3 ]

18 2012 MAXIM 18 Outline  Ionizing Radiation Environment and Damage Processes  Total Ionizing Dose Effects in CMOS  Effects in Bulk CMOS  Effects in SOI CMOS  Total Ionizing Dose Effects in Bipolar Technologies  Effects in Bipolar Junction Transistors  Enhanced Low Dose Rate Sensitivity (ELDRS)  Modeling Approaches

19 2012 MAXIM 19 TID effects in bulk CMOS nn p Gate Body Drain Source Dielectric (e.g., SiO 2 ) nn p Gate Body Drain Source +++++++ defects TID defect buildup in CMOS devices can degrade “as drawn” device characteristics create edge leakage parasitics in parallel with “as-drawn” device create inter-device leakage paths in bulk integrated circuits

20 2012 MAXIM 20 N ot effects on threshold voltage Oxide charge shifts flatband voltage  N ot

21 2012 MAXIM 21 N ot effects on MOSFET I-V Trapped holes in contribute net positive charge in the oxide, leading to a parallel, negative shift in MOSFET I-V characteristics (N ot )

22 2012 MAXIM 22 N ot Effects on 1/f noise (after Meisenheimer and Fleetwood, IEEE TNS 1990) Trapped holes near interface can act as slow “border” traps that exchange charge with semiconductor and increase 1/f noise

23 2012 MAXIM 23 N it effects on surface potential (p-channel example) Interface traps reduce surface potential sensitivity to gate bias between flatband and threshold

24 2012 MAXIM 24 N it effects on MOSFET I-V Traps cause increase in subthreshold swing, threshold voltage shifts, and reduced drive current via mobility degradation

25 2012 MAXIM 25 Dependence on dielectric thickness TID threat in modern bulk CMOS is defect buildup in thicker field oxides  V T = qNotqNot  ox (After Lacoe, IEEE REDW 2001) t ox - q  N it  ox t ox  N ot  t ox X Dose  V T /t ox 2  Dose

26 2012 MAXIM 26 Primary TID Threat in sub-micron CMOS TID defect build-up in “thick” isolation oxides (LOCOS or STI) create edge and inter-device leakage parasitics in bulk ICs STI Gate oxide halo implants n+ source n+ drain p-body STI > 300 nm < 3 nm Trapped charge buildup in STI

27 2012 MAXIM 27 Leakage Paths 1 2 3 1 2 3 NMOS Drain-to-Source NMOS D/S to NMOS S/D NMOS D/S to NWELL CMOS inverters 4 NWELL to NWELL (assume separate bias) 4

28 2012 MAXIM 28 Drain-to-Source Edge Leakage Increasing total dose

29 2012 MAXIM 29 Inter-device Leakage n+ D/S to n-welln+ D/S to n+ D/S Charge build-up in STI base

30 2012 MAXIM 30 Degradation in SRAM Measurements in SRAM show increased supply current after radiation exposure Cause: Positive charge buildup in trench isolation causing leakage currents between n-type regions. (after Clark et al., IEEE TNS 2007) Drain-source

31 2012 MAXIM 31 Outline  Ionizing Radiation Environment and Damage Processes  Total Ionizing Dose Effects in CMOS  Effects in Bulk CMOS  Effects in SOI CMOS  Total Ionizing Dose Effects in Bipolar Technologies  Effects in Bipolar Junction Transistors  Enhanced Low Dose Rate Sensitivity (ELDRS)  Modeling Approaches

32 2012 MAXIM Silicon on Insulator (SOI) MOS n+n+ n+n+ p Front Gate Source Drain Back Gate G ox Buried Oxide (B ox ) P-sub Key Advantages: Reduced junction capacitance V T control via dual gate operation t ox t Si t box t SUB 32

33 2012 MAXIM TID Effects in SOI n+n+ n+n+ p Source Drain Back Gate B ox P-sub t ox t Si t box t SUB +++++++ Negligible defect buildup in thin G ox Defect buildup Much of SOI TID susceptibility due to defect buildup in thick buried oxide (B ox ) t ox < 5 nm t box > 80 nm 33

34 2012 MAXIM TID Effects in SOI 34 Radiation damage to B ox can cause 1.Reduced frontgate V t caused by gate coupling 2.GIDL enhanced back- channel leakage 3.“Latch effect” due to non- uniform charge build-up and impact ionization (not discussed here) Negative V t shift with B ox thickness 80nm 140nm 380nm 410nm after Flament et al., IEEE TNS 2003

35 2012 MAXIM after Paillet et al., IEEE TNS 2005 Coupling Effect (Data) Front gate V t shift Fully depleted SOI devices with body contact can exhibit front-gate threshold voltage shift due to electrostatic coupling from back gate 35

36 2012 MAXIM Coupling Effect (Model) 36

37 2012 MAXIM GIDL Enhanced Leakage (Back-Channel) 37 High current at high total dose Drain current increase with negative gate bias via gate induced drain leakage (GIDL) enhancement after Schwank et al., IEEE TNS 2000

38 2012 MAXIM Mechanism for GIDL: band-to-band tunneling (BBT) 38 Local band-bending in high field drain-body region generates free carriers via electron tunneling After J-H Chen, IEEE TED 2001

39 2012 MAXIM GIDL Enhancement Mechanism 39 n+n+ n+n+ Source Drain Back Gate B ox P-sub Gate ++++++++++ Holes generated by BBT transport to source, forward biasing the source- body junction after Adell et al., IEEE NSREC 2007 - +

40 2012 MAXIM GIDL Enhancement Mechanism 40 n+n+ n+n+ Source Drain Back Gate B ox P-sub Gate ++++++++++ Holes generated by BBT transport to source, forward biasing the source- body junction Electrons back-injected into body increase electron concentration along back gate, enhancing back channel leakage after Adell et al., IEEE NSREC 2007 - +

41 2012 MAXIM GIDL Enhancement Mechanism (Band Effects) 41 Prior to radiation exposure and without BBT, back side interface is weakly depleted Trapped charge increases back- side surface potential, back channel concentration and current GIDL current increases electron Fermi level further raising back channel density and current

42 2012 MAXIM TID Effects in SOI Technologies: The BAD News 42  Charge buildup in the buried oxide continues to be a significant total ionizing dose threat in SOI technologies  The threats include:  Front gate threshold voltage reduction due to electrostatic coupling form the back gate.  Drain-to-source leakage caused by back-side inversion enhanced by GIDL and/or impact ionization (latch)  Traditional radiation-hardening-by-design techniques do not address the effects caused by damage to the B ox

43 2012 MAXIM TID Effects in SOI Technologies: The Good News 43  Commercial manufacturers typically increase doping along the back channel to reduce static power in CMOS circuits. This may mitigate the impact of charge buildup in the B ox  The use of body ties not only improves SEE effects in SOI parts but there is strong evidence that they also suppress latching and GIDL enhancement  Some commercial manufacturers reduced body lifetime thereby reducing diffusion lengths, which suppresses bipolar action, a principle mechanism in latching and GIDL enhancement

44 2012 MAXIM 44 Outline  Ionizing Radiation Environment and Damage Processes  Total Ionizing Dose Effects in CMOS  Effects in Bulk CMOS  Effects in SOI CMOS  Total Ionizing Dose Effects in Bipolar Technologies  Effects in Bipolar Junction Transistors  Enhanced Low Dose Rate Sensitivity (ELDRS)  Modeling Approaches

45 2012 MAXIM 45 PN Junctions The PN junction is a fundamental structure for BJTs

46 2012 MAXIM PN Junctions When forward biased (V AC > 0V), recombination (R) is maximized within the depletion region Depl. region x x R 46

47 2012 MAXIM Interface traps increase the recombination rate Depl. region x x R X X X X X X X X X X X Interface Trap Effects 47

48 2012 MAXIM Fixed positive charge in the oxide enhances recombination by increasing depl. region Depl. region x x R X X X X X X X X X X X Fixed Oxide Charge Effects + + + + + + For lighter doped p-region recombination increases super-linearly with dose 48

49 2012 MAXIM Trap defects will also increase generation (G) in reversed biased junctions (V AC < 0V) Depl. region x x G X X X X X X X X X X X Reverse Bias Generation + + + + + + 49

50 2012 MAXIM Bipolar Junction Transistors N P-substrate emitterbasecollector Current V be Base current Collector current 50

51 2012 MAXIM BJT Radiation Response Base-emitter voltage [V] Collector and base current [A] Base current increases when BJTs are irradiated Main reason for reduced current gain with radiation Increasing radiation dose What are the mechanisms for excess base current? After Kosier et al., IEEE Trans. Nucl. Sci., 1993 51

52 2012 MAXIM TID Effects in NPN BJTs N ot (+) depletes the p-type base surface, increasing area of recombination (depletion region) N it (X) increases surface recombination In PNP BJTs, base current is primarily of function of N it buildup alone ++++++++++++++++++++ n+n+ p-base n-collector emitter depletion region X X X X X X X X X N ot N it 52

53 2012 MAXIM Enhanced Low Dose Rate Sensitivity (ELDRS) After Witczak et al, IEEE Trans. Nucl. Sci., 1998 53 BJTs show enhanced sensitivity to TID when exposed at lower dose rates This phenomenon is known as Enhanced-Low-Dose- Rate- Sensitivity (ELDRS) ELDRS radiation bias dependence an important signature of its causes

54 2012 MAXIM 54 Potential Causes of ELDRS After Shaneyfelt et al., IEEE Trans. Nucl. Sci., 2002 Besides radiation bias, both pre-irradiation elevated temperature stress (PETS) and IC passivation impact ELDRS

55 2012 MAXIM 55 Effect of hydrogen on ELDRS The transition dose rates and low dose rate saturation limit can be changed by H 2 concentration in the oxide

56 2012 MAXIM 56 Outline  Ionizing Radiation Environment and Damage Processes  Total Ionizing Dose Effects in CMOS  Effects in Bulk CMOS  Effects in SOI CMOS  Total Ionizing Dose Effects in Bipolar Technologies  Effects in Bipolar Junction Transistors  Enhanced Low Dose Rate Sensitivity (ELDRS)  Modeling Approaches

57 2012 MAXIM 57 Modeling Radiation and Reliability Effects in Circuits Step 1 Construct transistor degradation functions Step 2 Model Transistor BTI response (Analytical, SPICE TCAD) Model Transistor BTI response (Analytical, SPICE TCAD)  Not,  Dit If  N ot and  D it are able to be measured experimentally as a function of bias stress and time, can their effects be simulated in SPICE at the circuit level? Techniques: Adjust parameters in the compact model, e.g., BSIM3v3 Apply external sources with defect generators that are functions of bias stress and time.

58 2012 MAXIM BSIM3v3 Compact Model Subthreshold Current Strong Inversion Current From BSM3 V3.2 Model Manual August 21, 1998 The drain current expression in both the subthreshold and strong inversion regimes are functions of V gs – V th for nFETs or V sg + V th for pFETs. N ot modeled by shift in V th0 D it modeled by shift in C it 58

59 2012 MAXIM Modeling Effects of Defects Parametric Adjustment of Compact Model No N ot and D it N ot = 1.2x10 12 cm -2 ; D it = 10 12 cm -2 /eV.MODEL PMOD PMOS (LEVEL=11 TOX=5e-9 K1=0 K2=0 NCH=5E17 NSUB=5E17 VTH0=-0.4631 IS=1E-18 +VOFF=-.055 U0=300 NFACTOR=1 NLX=0 K3=0 DVT0W=0 DVT0=0 ETA0=0 ETAB=0 UA=0 UB=0 UC=0 +JSGBR=1E-8 JSDBR=1E-8 JSGSR=1E-8 JSDSR=1E-8 JSGGR=1E-8 JSDGR=1E-8 DIOMOD=0 PSCBE1=0 PSCBE2=0 +BF=.0001 CIT=0).MODEL PMOD PMOS (LEVEL=11 TOX=5e-9 K1=0 K2=0 NCH=5E17 NSUB=5E17 VTH0=-0.8473 IS=1E-18 +VOFF=-.055 U0=300 NFACTOR=1 NLX=0 K3=0 DVT0W=0 DVT0=0 ETA0=0 ETAB=0 UA=0 UB=0 UC=0 +JSGBR=1E-8 JSDBR=1E-8 JSGSR=1E-8 JSDSR=1E-8 JSGGR=1E-8 JSDGR=1E-8 DIOMOD=0 PSCBE1=0 PSCBE2=0 +BF=.0001 CIT=1.6e-3) Modifications to SPICE model provide reasonable fit/ To experimental data but … 59

60 2012 MAXIM Modeling Effects of Defects Parametric Adjustment of Compact Model.MODEL PMOD PMOS (LEVEL=11 TOX=5e-9 K1=0 K2=0 NCH=5E17 NSUB=5E17 VTH0=- 0.8473 IS=1E-18 +VOFF=-.055 U0=300 NFACTOR=1 NLX=0 K3=0 DVT0W=0 DVT0=0 ETA0=0 ETAB=0 UA=0 UB=0 UC=0 +JSGBR=1E-8 JSDBR=1E-8 JSGSR=1E-8 JSDSR=1E-8 JSGGR=1E-8 JSDGR=1E-8 DIOMOD=0 PSCBE1=0 PSCBE2=0 +BF=.0001 CIT=1.6e-3) … how can temporal information about defects be readily incorporated into BSIM compact model files (provided in PDKs) without significant modifications to tools? THIS IS A PROBLEM FOR THE DESIGNERS! 60

61 2012 MAXIM Modeling Effects of Defects Ext. voltage sources w/ defect generators Is it possible to utilize external voltages (  V) in series with the transistor gate stimulus that mimic effects of time and bias dependent defects? Concept (sub-Vt example) Similar concept would be valid for BSIM strong inversion current equations Pre-stress vendor model Post-stress model Post-stress model = Pre-stress model w/ stress- induced offset VGVG VDVD IDID VV VG*VG* BSIM compact model for xstor is not modified Defect generator 61

62 2012 MAXIM Modeling Effects of Defects External sources with defect generators N ot = 1.5x10 12 cm -2 ; D it = 1.2X10 12 cm -2 /eV Use of external sources produces equally (compared to compact model adjustment) accurate simulation of effect of defects in DC External source ckt can be made into subcircuit and fixed in series with gate contact and external gate voltage. 62

63 2012 MAXIM Full NBTI Simulation P-channel MOSFET Drain Current Full p-channel simulation shows how drain current decays as a result of defect buildup during transient gate stress. 63

64 2012 MAXIM Full PBTI Simulation N-channel MOSFET Drain Current Time-dependent defect profile Impact of Not on n-channel offset by Dit during PBTI in n-channel (for the temporal defect profile selected). This may have an important effect on the balance between n- and p-channels in inverters and other logic cells. 64

65 2012 MAXIM Inverter Modeling propagation delay Increased high to low propagation delay with stress. 65

66 2012 MAXIM Inverter Modeling charge/discharge current Reduced charging current from p-channel cause of decreased performance 66

67 2012 MAXIM 92 MHz (unstressed) 84 MHz (stressed) Ring Oscillator Modeling (transient and frequency response w/ w/o stress) Ring Oscillator Circuit (twenty-three elements) 67 Transient Response No stress With stress Frequency Response

68 2012 MAXIM Modeling Summary 68 Technique enables: Effects of defects to be captured in time domain without modification to post-fabrication (vendor supplied) compact model. Density vs. time functions to be incorporated as defect generators. Simulates effect of time dependent stress in circuits.


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