1. Total Ionizing Dose Effects in Silicon Technologies and Devices
Hugh Barnaby, Philippe Adell*, Jie Chen, Michael Mclain, Ivan Sanchez, Harshit Shah
Arizona State University
*Jet Propulsion Laboratory

2. Topics
Modeling total ionizing dose effects in deep submicron bulk CMOS technologies - Hugh Barnaby, ASU
Band-to-band tunneling (BBT) induced leakage current enhancement in irradiated fully depleted SOI devices - Philippe Adell, JPL
Mechanisms of enhanced radiation-induced degradation due to excess molecular hydrogen in bipolar oxides - Jie Chen, ASU

3. Modeling Total Ionizing Dose Effects in Deep Submicron Bulk CMOS technologies
Hugh Barnaby, Michael Mclain, Ivan Sanchez, Harshit Shah
Department of Electrical Engineering
Ira A. Fulton School of Engineering
Arizona State University

4. ASU task
Characterize and model TID effects in bulk deep submicron CMOS devices
Design and build radiation-enabled compact models
Technologies: deep sub-micron bulk CMOS, silicon on insulator, device isolation structures (STI, BOX)

5. Hot Carrier Limit Region
Reliability threats
Hot Carrier Limit Region
ITRS Roadmap
250nm
180nm
130nm
NBTI Limit Region 2 3 4 5
Oxide Thickness (nm) 1
Supply Voltage (V)
Traditional:
Hot-Carrier-Injection (HCI)
Nanoscale roadblock:
Negative-bias-temperature-instability (NBTI)
Other issues:
TDDB, etc.
after N. Kimizuka et al., VLSI Tech. 1999

6. Radiation threats in bulk CMOS
Radiation damage in shallow trench oxides increases leakage
Intra-device leakage
Inter-device leakage

7. TID Defects Not, Nit a tox Defects Not - oxide trapped charge (E’ )
Nit – interface traps (Pb)
Both Nit and Not are related to holes generated and/or hydrogen present in oxide
first order assumption
Not, Nit a tox

8. Research Goal
To develop a compact modeling approach that can simulate and predict the effects of stress and radiation damage of semiconductor devices and circuits?

9. Research Goal
To develop a compact modeling approach that can simulate and predict the effects of stress and radiation damage of semiconductor devices and circuits?
This capability, known as Predictive Technology Modeling (PTM), has been demonstrated for modeling negative bias temperature instability.

10. Predictive technology modeling (PTM)
The goal of PTM is to develop compact modeling approaches that are:
Scalable with technology and design parameters
Capable of both short-term and long-term predictions
Compatible with standard circuit simulator
Extendable to emerging reliability and radiation effects concerns

11. PTM Approach (for NBTI)
Model validation path
Circuit simulation with ageing effects
Modeling inputs

12. Model validation Model verified with published silicon data
180nm, VLSI, 1999
Tox=2.6nm, T=125oC
Vgs=2.9V, T=100oC
130nm, IRPS, 2003
n=0.25
Excellent scalability over process and design conditions
After Vattikonda et al. DAC 2006.

13. Research Goal
To develop a compact modeling approach that can simulate and predict the effects of stress and radiation damage of semiconductor devices and circuits?
This capability, known as Predictive Technology Modeling (PTM) has already been demonstrated for modeling negative bias temperature instability at ASU.
Our goal is to extend PTM for reliability to capture radiation effects

14. PTM Approach (for TID) Radiation-enabled circuit simulation
Modeling inputs

15. Radiation-enabled PTM (Physical Module)
Inputs
Physical
Module
Output (defects)
Model validation

16. Closed form model for TID
Oxide trapped charge dependence on dose, oxide field and thickness.
Interface trap dependence on dose, oxide field and thickness.
Model Parameters
Models based on assumptions of steady state, uni- directional flux, and no saturation or annealing
D - total dose [rad]
kg x 1012 [ehp/radcm3]
fy - field dependent hole yield [hole/ehp]
fot - trapping efficiency [trapped hole/hole]
fDH - hole, D’H reaction efficiency [H+/hole]
fit - H+, SiH de-passivation efficiency [interface trap/H+]
tox - oxide thickness [cm]
Technology Computer Aided Design (TCAD) tools provide simulation capability at the process, device, and circuit level. This slide illustrates the relationship between the different levels of simulation in standard TCAD tools (without including radiation effects). Process simulations begin with inputs including times, temperatures, and ambient environments and yield structural information including doping profiles and layer thicknesses. The device simulator takes this information, along with bias conditions, to provide externally-measurable properties like current-voltage characteristics and internal quantities like potential and electric field. The circuit simulator calculates the behavior of a collection of interconnected devices using compact models of the device current-voltage and transient characteristics.
See Barnaby, MURI presentation 2006

17. Simple Model – Not(x) + + The simple model requires: STIVg
The simple model requires:
Doping distribution along sidewall to generate NA(i) and fMS(i) arrays
Field line estimates to generate tox(i) and eox(i) arrays
Vgb bias condition
tox(i)
eox(i)
x(i) +
NA(i) +
x(i+1)
STI
… to compute the e-field. x Vb
E-field a function of Not (iterative)
Surface potential
Technology Computer Aided Design (TCAD) tools provide simulation capability at the process, device, and circuit level. This slide illustrates the relationship between the different levels of simulation in standard TCAD tools (without including radiation effects). Process simulations begin with inputs including times, temperatures, and ambient environments and yield structural information including doping profiles and layer thicknesses. The device simulator takes this information, along with bias conditions, to provide externally-measurable properties like current-voltage characteristics and internal quantities like potential and electric field. The circuit simulator calculates the behavior of a collection of interconnected devices using compact models of the device current-voltage and transient characteristics.

18. Non-uniform doping In deep submicron CMOS,
Sidewall doping
In deep submicron CMOS,
the doping along the sidewall is highly non-uniform
Technology Computer Aided Design (TCAD) tools provide simulation capability at the process, device, and circuit level. This slide illustrates the relationship between the different levels of simulation in standard TCAD tools (without including radiation effects). Process simulations begin with inputs including times, temperatures, and ambient environments and yield structural information including doping profiles and layer thicknesses. The device simulator takes this information, along with bias conditions, to provide externally-measurable properties like current-voltage characteristics and internal quantities like potential and electric field. The circuit simulator calculates the behavior of a collection of interconnected devices using compact models of the device current-voltage and transient characteristics.

19. TCAD Modeling 1 krad 10 krad 100 krad
TCAD modeling with the Silvaco REM simulator can generate volumetric distributions of trapped charge in the STI (for model validation).
1 krad
10 krad
100 krad

20. Not estimates
Vgb = 1V
100 krad
10 krad
Vgb = 0V
10krad dose
1 krad
Vgb = 0V
Simulator predicts dose and bias dependence (as well as temperature, dose rate, etc.).

21. Radiation-enabled PTM (Compact modeling)

22. Compact Modeling for TID (surface potential)
Nit, Not
from phys.
mod.
ys(x,y)
Surface potential information is used in the PSP compact model being developed and refined at ASU.

23. Compact Modeling for TID (drain-source leakage)
MR2
MR1
Effect of charge buildup along STI sidewall degrades can be modeled as two parasitic nMOSFETs (MR1 and MR2) operating in parallel with as drawn device, MA.D.

24. D-S leakage model using BSIM4 compact model
MR1
Parameters in modified BSIM4 model enables parasitic devices to be modeled
MR2
model nfetMR1_10MRAD bsim4 type=n (W=50.1nm L=120nm)
+ tnom = toxe = 12.46e toxp = 1.1e-9
+ rnoia = rnoib = vth0 =
+ cdsc = cdscb = 0 cdscd = 0 cit =
+ + u = ua = 1e-10 ub = 4e-16
+ ……
MA.D.

25. Modeling bias dependence with BSIM4

26. Circuit Level Modeling (A/D Converter)
Flash-type ADC
Compact (C-) models, degraded as function of dose and radiation bias, are used by EDA tools to model circuit degradation over time.
C-models can be inserted at the circuit-level (SPICE/SPECTRE) or in higher level behavioral models for increased efficiency.

27. Circuit Level Modeling (results)
Modeled application response to intra-device leakage under static radiation bias conditions
Radiation dose
Input voltage
Output
after Mikkola et al. RADECS 2006