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Tutorial 3 VLSI Design Methodology Boonchuay Supmonchai June 10th, 2006.

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Presentation on theme: "Tutorial 3 VLSI Design Methodology Boonchuay Supmonchai June 10th, 2006."— Presentation transcript:

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2 Tutorial 3 VLSI Design Methodology Boonchuay Supmonchai June 10th, 2006

3 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 2 Outlines  VLSI Design Flow and Structural Design Principles  VLSI Design Styles  VLSI Design Strategies  Computer-Aided Design Technology for VLSI

4 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 3 Simplified VLSI Design Flows System Specification Functional (Architecture) Design Functional Verification Logic Design Logic Verification Circuit Design Circuit Verification Physical Design Physical Verification Front End Back End Synthesis Phase Layout Phase BehavioralRepresentation Logic(Gate-Level)Representation CircuitRepresentation LayoutRepresentation

5 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 4 Four Levels of Design Representation BehavioralRepresentation Logic (Gate-Level) Representation Circuit(Transistor-Level)Representation LayoutRepresentation Functional Blocks, FSM Logic Blocks, Gates Transistor Schematics Physical Devices

6 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 5 Structure Design Principles  Hierarchy  Hierarchy:  “Divide and conquer”  “Divide and conquer” technique involves dividing a module into sub-modules and then repeating this operation on the sub- modules until the complexity of the smaller parts becomes manageable.  Regularity  Regularity: simplesimilar  The hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible.  Regularity usually reduces the number of different modules that need to be designed and verified, at all levels of abstraction.

7 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 6 Example of Regularity These circuits are built using inverters and tri-state buffers only.

8 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 7 Structured Design Principles (Cont.)  Modularity  Modularity: well-defined functionsinterfaces.  The various functional blocks which make up the larger system must have well-defined functions and interfaces.  Modularity allows each block to be designed independently; All blocks can be combined with ease at the end of the process.  Locality  Locality:  Internal details remain at the local level. avoiding long-distance connections  The concept of locality also ensures that connections are mostly between neighboring modules, avoiding long-distance connections as much as possible.

9 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 8 Example: 16-bit Adder Circuit Structural Hierarchy of a 16-bit Manchester Adder

10 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 9 Example (Cont.): Level 1 16-bit Adder Complete Layout 4-bit Adder with Manchester carry

11 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 10 Example (Cont.): Level 2 4-bit Adder with Manchester Carry Layout Carry/propagate circuit Output buffer/latch Manchester Carry circuit

12 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 11 Example (Cont.): Level 3 Carry/propagate circuit layout Manchester carry circuit layout Output buffer/latch circuit layout

13 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 12 Outlines  VLSI Design Flow and Structural Design Principles  VLSI Design Styles  VLSI Design Strategies  Computer-Aided Design Technology for VLSI

14 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 13 VLSI Design Styles

15 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 14 Full-Custom Design  Full-custom blocks are carefully crafted in the physical level to obtain the highest possible performance.

16 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 15 Full-Custom Design Key Issues  The key to Full-custom design is to exploit the fine-grained regularity and modularity in the physical level.  Manual full-custom design can be very challenging and time consuming, especially if the low level regularity is not well defined.  Development cost are too high! IP blocks  Design reuse is becoming popular to reduce design cycle time and development cost.  IP blocks  Full-custom design is used only in the critical blocks.

17 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 16 Full-Custom DRAM Example

18 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 17 Cell-Based Design  “Lego” Style Design  All of the commonly used logic cells are developed, characterized, and stored in a standard cell library.  Library contains a certain numbers of basic cells such as inverters, NAND, NOR, each in several versions to provide a range of performance.  The inverter gate can have standard size, double size, and quadruple size.  Most popular because of CAD tools availability and capability.

19 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 18 Cell-Based Design Key Issues  Inclusion/Exclusion of a gate variation depends on the objectives of the library.  Standard Library, Low Power Library, etc.  Most challenging task is to how to place the individual cells into rows and interconnect them in a way that meet stringent design goals.  Most advanced CAD tools have place-and-route tools.  In a complex, demanding design, standard-cell based design approach may be used as a first pass, then full-custom design where necessary.

20 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 19 Example of Standard Cells Each cell layout is designed with a fixed height so that a number of cells can be “snapped” together side-by-side to form rows. Power Rail Ground Rail

21 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 20 Example of Stand Cells (Cont.) Standard Cell Routing Channel

22 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 21 Cell-Based Design Example

23 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 22 Masked Gate Array (MGA) Design Only transistors No contacts and metal layers One pattern mask for Mass production

24 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 23 MGA Design Key Issues  “Uncommitted” (Unused) transistors or gates are wasted.  Performance measured as Chip Utilization Factor ~ used chip area/total chip area.  Uncommitted cells can be sacrifices to improve intercell routing capability  Modern GAs use multiple metal layers for channel routing  Smaller area, higher density, and routability

25 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 24 Example of MGA Design

26 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 25 FPGA Design  An FPGA chip provides thousands of logic gates, organized into logic blocks, with programmable interconnects.  To implement a custom hardware, a user can use high-level hardware programming (e.g., HDL).  Program logic table for each logic block.  Program interconnect switch matrices  Program I/O blocks  Programs last as long as the chip is powered-on

27 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 26 Field Programmable Gate Array (FPGA) Architecture of Xilinx FPGAs

28 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 27 FPGA (Cont.) Simplified block diagram of a CLB by Xilinx

29 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 28 FPGA (Cont.) Switch matrices and interconnection routing between CLB

30 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 29 FPGA Design Key Issues  Chip utilization of an FPGA depends on  Granularity  Granularity of the logic block - Size of logic block  Routing capability  Routing capability - Size of switch matrices turn-around time  The largest advantage of FPGA-based design is the very short turn-around time  The time required from the start of the design process until a functional chip is available  Typical price of FPGA chips is usually higher than other alternatives of the same design, but for small-volume production and for fast prototyping

31 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 30 HDL-Based Design 1980’s Hardware Description Languages (HDL) were conceived to facilitate the information exchange between design groups. 1990’s The increasing computation power led to the introduction of logic synthesizers that can translate the description in HDL into a synthesized gate-level net-list of the design. 2000’s Modern synthesis algorithms can optimize a digital design and explore different alternatives to identify the design that best meets the requirements.

32 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 31 HDL-Based Design Methodology

33 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 32 Outlines  VLSI Design Flow and Structural Design Principles  VLSI Design Styles  VLSI Design Strategies  Computer-Aided Design Technology for VLSI

34 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 33 VLSI Design Strategies  Phenomenal growth rate in VLSI leads to a very complex and lengthy development of ICs. exponentially  Design complexity increases almost exponentially with the number of transistors to be integrated.  Efficient organization of all efforts is essential to the survival of a company.  Teamwork  Better tools  Innovatives and creativities.  Better Strategies

35 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 34 Product Life-Cycle Products have a shorter life-cycle

36 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 35 Comparison of Design Strategies Freedom of Choices…. Custom Design

37 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 36 Comparison (Cont.) Cell Design FPGA Design

38 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 37 System-On-Chip (SOC) Design  Integrating all or most of the components of a hybrid system on a single substrate (silicon or MCM), rather than building a conventional printed circuit board.  Consequences:  More compact system realization  Less expensive!  Higher speed / performance  Better reliability

39 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 38 Example of SOC Design Digital Video Processor

40 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 39 Example of SOC Design (Cont.) Each functional block can be reused block, IP (Intelectual Property) block, or custom-designed block.

41 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 40 Outlines  VLSI Design Flow and Structural Design Principles  VLSI Design Styles  VLSI Design Strategies  Computer-Aided Design Technology for VLSI

42 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 41 Computer-Aided Design Technology  CAD tools become more and more indispensable for timely development of ICs. CAD tools are good helpers for time-consuming and computation intensive mechanistic parts of the design, not the creative and inventive parts!  Remember!  CAD tools are good helpers for time-consuming and computation intensive mechanistic parts of the design, not the creative and inventive parts!  CAD technology divides into three categories:  Synthesis Tools (Synopsys®)  Layout Tools (Cadence®)  Simulation and Verification Tools

43 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 42 Synthesis Tools  High-Level Synthesis  High-Level Synthesis tools automate the design phase in the top level of the design hierarchy:  Based on Hardware-Description Languages (HDL)  VHDLVerilog  VHDL, Verilog, etc.  Determining the types and quantities of modules to be included in the design using accurate estimate of lower level design features (area and delay).  Logic Synthesis and optimization  Logic Synthesis and optimization tools can then be used to customize the design to particular needs, such as area minimization, low power, etc.

44 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 43 Layout Tools  Circuit Optimization  Circuit Optimization tools deal with the design in the transistor schematic levels:  Transistor sizing for delay minimization  Reliability issues: process variations, noise.  Layout  Layout tools concern with the physical level of the design, i.e., how circuits are actually built on the IC:  Standard Layout CAD tools are Floorplanning, Place-and-route, and Module generation  Sophisticated Layout CAD tools are goal driven and include some degree of optimization functions

45 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 44 Simulation and Verification Tools exponentially  Time spent on debugging and correcting a design has been increasing exponentially as each generation passed.  Higher penalty is paid if a design flaw is detected later in the design process.  Simulation and verification are the most mature area in VLSI CAD  Goal of all simulation tools is to determine if the design meets the required specifications at a particular design stage.

46 B.Supmonchai 2102545 Digital IC VLSI Design Methodology 45 Simulation Tools (Cont.)  Simulation tools used at various stages of the design process are  Behavior simulation  Behavior simulation tools  Logic Level simulation  Logic Level simulation tools  Complement logic synthesis and optimization tools.  Circuit-level simulation  Circuit-level simulation tools  SPICE or derivatives such as HSPICE, PSPICE, etc.  Design Rule Checking  Design Rule Checking tools Electrical Rule Checking  Layout rule checking, Electrical Rule Checking (ERC), reliability rule checking.

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