1. Quartus II Schematic Design Tutorial Xiangrong Ma max6@unlv.nevada.edu

2. Design Flow

3.  Project information  Directory  Project name  Top level name  Device  Select Cyclone  (small & fast for compile) Create Project

4.  Create a new Schematic File  Add Gates  Add Pins  Check Design Design Capture

5.  Fix Errors  Check Reports Compile(Synthesis & Fit & STA)

6.  Create a waveform vector File  Add input/output pins(using Node Finder)  Change value for input pins  Keep outputs as “X” Create test stimulus file

7.  Right Click on Project,  choose “Settings”  Select “Simulator Setting”  Select input file  Select Simulation mode  Functional  timing Setup Simulation Environment

8.  Functional Simulation  Generate Functional netlist file for simulation  0 delay, just “functional”  Timing Simulation  After Compilation, timing information was extracted from devices  Wire delay/logic delay information would be used for “back-annotated simulation”  Much more accurate Generate Netlist

9. Run Simulation

10.  Fix errors Analysis S=A and B C=A or B S=A and B C=A or B

11. .qpfQuatus Project File .qsf Quatus Setting File .vwfVector Waveform File .bdfBlock Design File .rptReport File extension description

12.  Quartus II 7.2 Web Edition(sp3) URLs https://www.altera.com/download/quartus-ii-we/dnl-quartus_we-v72.jsp