1. Nios II Processor-Based Self- Adaptive QRS Detection System Institution: Indian Institute of Technology, Kharagpur Participants: Sai Prashanth, Prashant Agrawal Instructor: Professor Agit Pal December 9, 2011RPR1

2. Outline Background Project Outline FPGA Design Signification Functional Description Plot Architecture QRS Detection Results ECG Hardware Block Diagram Software QRS Detection Algorithm Flow Chart Design’s Implementation steps Conclusion December 9, 2011RPR2

3. Background QRS detection provides the fundamental for almost all ECG analysis algorithm Software QRS detection -Based on signal processing techniques -An asymptotic detection performance Choosing the QRS detection algorithm best suited to the current context is an essential step in the development of a real-time ECG analysis system December 9, 2011RPR3

4. Project Outline Algorithm-bank-based solutions -Periodic sampling of the input ECG signal -Dynamic decision to find the most appropriate algorithm December 9, 2011RPR4 Reduction of the number of errors SAMPLER Altera Nios II Processor (CPU0) ANALYZER Altera Nios II Processor (CPU1) ADC ECG Patient Context Arrhythmia Fig.2: The design overview of ECG monitoring system Sub-units within the scope of this project

5. Project Outline December 9, 2011RPR5 SAMPLER Altera Nios II Processor (CPU0) ANALYZER Altera Nios II Processor (CPU1) ECG Patient Context Arrhythmia Acquisition, context analysis, and piloting of the analyzer The actual QRS complex detection and medical diagnosis Fig.2: The design overview of ECG monitoring system ADC Implemented using the Altera Nios®II processor

6. FPGA Design Significance The trend in embedded system design -Implementing entire functional system on a single chip The advent of high-density FPGA have enabled designers to implement a complete system on a chip Benefits -Portable, cost effective, and low power consumption (compared to PCs) -Complex ICs with millions of gates are now available -Performing control and decision making operation efficiently -Performing DSP operations and other computationally intensive tasks -SOPC Builder integrates complex system components such as IP blocks, memories, and interfaces to off-chip devices -The Altera Nios II processor supports HW/SW co-design and multi-core processing December 9, 2011RPR6

7. Functional Description December 9, 2011RPR7 ANALYZER (Nios II Processor, CPU1) SAMPLER (Nios II Processor, CPU0) ADC Line Context Analyzer Patient Context PILOT Arrhythmia Context Analyzer Chronicle Recognition Rule Base Chronicle BaseAlgorithm Bank Temporal Abstraction FilteringQRS Classification QRS DetectionP-wave Detection ECG Arrhythmia Fig.3: ECG Medical Monitoring System

8. Functional Description December 9, 2011RPR8 ANALYZER (Nios II Processor, CPU1) SAMPLER (Nios II Processor, CPU0) ADC Line Context Analyzer Patient Context PILOT Arrhythmia Context Analyzer Chronicle Recognition Rule Base Chronicle BaseAlgorithm Bank Temporal Abstraction FilteringQRS Classification QRS DetectionP-wave Detection ECG Arrhythmia Fig.3: ECG Medical Monitoring System Temporal abstraction is composed of four linked tasks

9. Functional Description December 9, 2011RPR9 ANALYZER (Nios II Processor, CPU1) SAMPLER (Nios II Processor, CPU0) ADC Line Context Analyzer Patient Context PILOT Arrhythmia Context Analyzer Chronicle Recognition Rule Base Chronicle BaseAlgorithm Bank Temporal Abstraction FilteringQRS Classification QRS DetectionP-wave Detection ECG Arrhythmia Fig.3: ECG Medical Monitoring System Four tasks are performed by shortest path (SP) algorithm

10. Pilot Architecture December 9, 2011RPR10 Current Context Line Context Patient Context Arrhythmia Context Context Manager Chronicle Model Choice Rules Task Choice Rules SP Piloting Rules Arrhythmia Recognition Level Interface Engine Temporal Abstraction Tasks Level Interface Engine SP Algorithm Level Interface Engine Chronicle Models to Use Task to Activate and Deactivate SP Algorithm to Tune Manager Rules

11. QRS Detection Results ECG Score Ne 1Ne 2Ne 3Ne 4Ne 5Total NeEr (%) Pan*20*91*240*312*3671,03014.3 Gritzali20*160388360*2951,22317 df2307278*174*160*3021,22117 Pilot208818516730476410.6 December 9, 2011RPR11 Five ECGs were generated from the MIT-BIH database Ne: The number of errors Er : The error rate (Er = Ne/NQRS, where NQRS is the total number of actual QRSs) The pilot chooses the best algorithm with the aid of the piloting rules In this study, the algorithm thresholds are optimal in the sense that Ne is minimum

12. ECG Hardware Block Diagram December 9, 2011RPR12 Keyboard ANALYZER (Nios II Processor Augmented with Custom Instructions) SAMPLER (Nios Coprocesspr) RAM LCD Display ADC ECG Data LCD Data Buffer Interrupt

13. Software QRS Detection Algorithm Flow Chart December 9, 2011RPR13 Selection of Characteristic Scales Determination of Modulus Maxima Lines of R Waves Calculation of Singular Degree Elimination of Isolated Modules Maxima Lines Detection of R Peak QRS Onset & Offset Detection T & P Wave Detection Elimination of Redundant Modulus Maxima Lines

14. Design’s Implementation Steps 1.Research and determine a set of complementary QRS detection algorithms and develop software algorithms to support them 2.Create a Quartus II project Compile and debug the project and review the compilation report and test the project 3.Create an algorithm bank consisting of four different QRS detection algorithms and test the performance December 9, 2011RPR14

15. Design’s Implementation Steps 4.Update the SOPC Builder processor configuration and optimize the processor until the desired performance requirement is met 5.Create interrupt-based interfaces using Nios II IDE and test these I/O interface 6.Test the ECG medical monitoring system performance and determine the error rates of the QRS complex detection December 9, 2011RPR15

16. Applying SOPC Concepts Compared to ASIC SOC, SOPC has many unique features The design uses SOPC concepts in the following ways Modular system design -The system is divided and simplified, which makes it easer to implement System integration - It is very difficult to implement highly integrated design without lowering the design target or using a different FPGA Various modes -Using SOPC concepts and excellent design tools enabled authors to use various mode Final system can be updated -The design can be flexible configured and updated during the design process December 9, 2011RPR16

17. Conclusion Using Nios II processor, it is possible to design their system easily, including dual-core embedded processors, on-chip and off-chip memory, and high-speed I/O ports Using SOPC Builder, it is possible to modify the CPU hardware at any time for multi-purpose development Altera’s ability to develop and update the Nios II processor and function was extremely important Using SOPC concepts allowed us to create a more flexible, dynamically reconfigurable, and computationally intensive implementation December 9, 2011RPR17

18. December 9, 2011RPR18

19. Functional Description December 9, 2011RPR19 ANALYZER (Nios II Processor, CPU1) SAMPLER (Nios II Processor, CPU0) ADC Line Context Analyzer Patient Context PILOT Arrhythmia Context Analyzer Chronicle Recognition Rule Base Chronicle BaseAlgorithm Bank Temporal Abstraction FilteringQRS Classification QRS DetectionP-wave Detection ECG Arrhythmia Fig.3: ECG Medical Monitoring System Separating the actual ECG signal from the noisy part of the signal

20. Functional Description December 9, 2011RPR20 ANALYZER (Nios II Processor, CPU1) SAMPLER (Nios II Processor, CPU0) ADC Line Context Analyzer Patient Context PILOT Arrhythmia Context Analyzer Chronicle Recognition Rule Base Chronicle BaseAlgorithm Bank Temporal Abstraction FilteringQRS Classification QRS DetectionP-wave Detection ECG Arrhythmia Fig.3: ECG Medical Monitoring System Identifying QRS occurrence dates

21. Functional Description December 9, 2011RPR21 ANALYZER (Nios II Processor, CPU1) SAMPLER (Nios II Processor, CPU0) ADC Line Context Analyzer Patient Context PILOT Arrhythmia Context Analyzer Chronicle Recognition Rule Base Chronicle BaseAlgorithm Bank Temporal Abstraction FilteringQRS Classification QRS DetectionP-wave Detection ECG Arrhythmia Fig.3: ECG Medical Monitoring System Labeling QRS morphologies

22. Functional Description December 9, 2011RPR22 ANALYZER (Nios II Processor, CPU1) SAMPLER (Nios II Processor, CPU0) ADC Line Context Analyzer Patient Context PILOT Arrhythmia Context Analyzer Chronicle Recognition Rule Base Chronicle BaseAlgorithm Bank Temporal Abstraction FilteringQRS Classification QRS DetectionP-wave Detection ECG Arrhythmia Fig.3: ECG Medical Monitoring System Identifying P wave occurrence dates

23. December 9, 2011RPR23