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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a1 Design for Testability Theory and Practice Lecture 4a: Simulation n What is simulation? n Design verification n Circuit modeling n True-value simulation algorithms n Compiled-code simulation n Event-driven simulation n Summary

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a2 Simulation Defined n Definition: Simulation refers to modeling of a design, its function and performance. n A software simulator is a computer program; an emulator is a hardware simulator. n Simulation is used for design verification: n Validate assumptions n Verify logic n Verify performance (timing) n Types of simulation: n Logic or switch level n Timing n Circuit n Fault (Lecture 4b)

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a3 Simulation for Verification True-value simulation Specification Design (netlist) Input stimuli Computed responses Response analysis Synthesis Design changes

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a4 Modeling for Simulation n Modules, blocks or components described by n Input/output (I/O) function n Delays associated with I/O signals n Examples: binary adder, Boolean gates, FET, resistors and capacitors n Interconnects represent n ideal signal carriers, or n ideal electrical conductors n Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy.

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a5 Example: A Full-Adder HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e); a b c d e f HA FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); HA1 HA2 A B C D E F Sum Carry Half-adder Full-adder

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a6 CaCa Logic Model of MOS Circuit CcCc CbCb V DD a b c pMOS FETs nMOS FETs C a, C b and C c are parasitic capacitances DcDc DaDa c a b D a and D b are interconnect or propagation delays D c is inertial delay of gate DbDb

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a7 Options for Inertial Delay (simulation of a NAND gate) b a c (CMOS) Time units 0 5 c (zero delay) c (unit delay) c (multiple delay) c (minmax delay) Inputs Logic simulation min =2, max =5 rise=5, fall=5 Transient region Unknown (X) X

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a8 Signal States n Two-states (0, 1) can be used for purely combinational logic with zero-delay. n Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. n Four-states (0, 1, X, Z) are essential for MOS devices. See example below. n Analog signals are used for exact timing of digital logic and for analog circuits. 0 0 Z (hold previous value)

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a9 Modeling Levels Circuit description Programming language-like HDL Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances Transistor technology data, connectivity, node capacitances Tech. Data, active/ passive component connectivity Signal values 0, 1 0, 1, X and Z 0, 1 and X Analog voltage Analog voltage, current Timing Clock boundary Zero-delay unit-delay, multiple- delay Zero-delay Fine-grain timing Continuous time Modeling level Function, behavior, RTL Logic Switch Timing Circuit Application Architectural and functional verification Logic verification and test Logic verification Timing verification Digital timing and analog circuit verification

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a10 True-Value Simulation Algorithms n Compiled-code simulation n Applicable to zero-delay combinational logic n Also used for cycle-accurate synchronous sequential circuits for logic verification n Efficient for highly active circuits, but inefficient for low- activity circuits n High-level (e.g., C language) models can be used n Event-driven simulation n Only gates or modules with input events are evaluated (event means a signal change) n Delays can be accurately simulated for timing verification n Efficient for low-activity circuits n Can be extended for fault simulation

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a11 Compiled-Code Algorithm n Step 1: Levelize combinational logic and encode in a compilable programming language n Step 2: Initialize internal state variables (flip-flops) n Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations) n Execute compiled code Report or save computed variables

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a12 Event-Driven Algorithm (Example) 2 2 4 2 a = 1 b = 1 c = 1 0 d = 0 e = 1 f = 0 g = 1 Time, t 0 4 8 g t = 0 1 2 3 4 5 6 7 8 Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 Activity list d, e f, g g Time stack

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a13 Efficiency of Event- Driven Simulator n Simulates events (value changes) only n Speed up over compiled-code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change Large logic block without activity Steady 0 0 → 1 event Steady 0 (no event)

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Copyright 2001, Agrawal & BushnellDay-1 PM Lecture 4a14 Summary n Logic or true-value simulators are essential tools for design verification. n Verification vectors and expected responses are generated (often manually) from specifications. n A logic simulator can be implemented using either compiled-code or event-driven method. n Per vector complexity of a logic simulator is approximately linear in circuit size. n Modeling level determines the evaluation procedures used in the simulator.

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