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1 Part I: SYSTEM DESIGN. 2 Packages and Components Functions and Procedures Problem (Design & Implementation) Additional System Designs.

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Presentation on theme: "1 Part I: SYSTEM DESIGN. 2 Packages and Components Functions and Procedures Problem (Design & Implementation) Additional System Designs."— Presentation transcript:

1 1 Part I: SYSTEM DESIGN

2 2 Packages and Components Functions and Procedures Problem (Design & Implementation) Additional System Designs

3 3 Packages and Components

4 4 PACKAGE PACKAGE package_name IS (declarations) END package_name; [PACKAGE BODY package_name IS (FUNCTION and PROCEDURE descriptions) END package_name;] PACKAGE package_name IS (declarations) END package_name; [PACKAGE BODY package_name IS (FUNCTION and PROCEDURE descriptions) END package_name;] 1.Code partitioning, 2.Code sharing, 3.and code reuse. 1.Code partitioning, 2.Code sharing, 3.and code reuse. Example: Simple Package 1 ------------------------------------------------ 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ------------------------------------------------ 5 PACKAGE my_package IS 6 TYPE state IS (st1, st2, st3, st4); 7 TYPE color IS (red, green, blue); 8 CONSTANT vec: STD_LOGIC_VECTOR(7 DOWNTO 0) := "11111111"; 9 END my_package; 10 ------------------------------------------------ PACKAGE BODY is not necessary

5 5 Example: Package with a Function 1 ------------------------------------------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ------------------------------------------------- 5 PACKAGE my_package IS 6 TYPE state IS (st1, st2, st3, st4); 7 TYPE color IS (red, green, blue); 8 CONSTANT vec: STD_LOGIC_VECTOR(7 DOWNTO 0) := "11111111"; 9 FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN; 10 END my_package; 11 ------------------------------------------------- 12 PACKAGE BODY my_package IS 13 FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN IS 14 BEGIN 15 RETURN (s'EVENT AND s='1'); 16 END positive_edge; 17 END my_package; 18 ------------------------------------------------- ------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.my_package.all; ------------------------------------ ENTITY...... ARCHITECTURE...... ------------------------------------ LIBRARY ieee; USE ieee.std_logic_1164.all; USE work.my_package.all; ------------------------------------ ENTITY...... ARCHITECTURE...... ------------------------------------

6 6 COMPONENT COMPONENT component_name IS PORT ( port_name : signal_mode signal_type;...); END COMPONENT; COMPONENT component_name IS PORT ( port_name : signal_mode signal_type;...); END COMPONENT; COMPONENT declaration: COMPONENT instantiation: label: component_name PORT MAP (port_list);

7 7 Example: Components Declared in the Main Code

8 8 1 ------ File inverter.vhd: ------------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ------------------------------------ 5 ENTITY inverter IS 6 PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC); 7 END inverter; 8 ------------------------------------ 9 ARCHITECTURE inverter OF inverter IS 10 BEGIN 11 b <= NOT a; 12 END inverter; 13 --------------------------------------------- 1 ------ File nand_2.vhd: --------------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ------------------------------------ 5 ENTITY nand_2 IS 6 PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC); 7 END nand_2; 8 ------------------------------------ 9 ARCHITECTURE nand_2 OF nand_2 IS 10 BEGIN 11 c <= NOT (a AND b); 12 END nand_2; 13 --------------------------------------------- 1 ----- File nand_3.vhd: ---------------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ------------------------------------ 5 ENTITY nand_3 IS 6 PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC); 7 END nand_3; 8 ------------------------------------ 9 ARCHITECTURE nand_3 OF nand_3 IS 10 BEGIN 11 d <= NOT (a AND b AND c); 12 END nand_3; 13 ---------------------------------------------

9 9 1 ----- File project.vhd: --------------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ------------------------------------ 5 ENTITY project IS 6 PORT (a, b, c, d: IN STD_LOGIC; 7 x, y: OUT STD_LOGIC); 8 END project; 9 ------------------------------------ 10 ARCHITECTURE structural OF project IS 11 ------------- 12 COMPONENT inverter IS 13 PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC); 14 END COMPONENT; 15 ------------- 16 COMPONENT nand_2 IS 17 PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC); 18 END COMPONENT; 19 ------------- 20 COMPONENT nand_3 IS 21 PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC); 22 END COMPONENT; 23 ------------- 24 SIGNAL w: STD_LOGIC; 25 BEGIN 26 U1: inverter PORT MAP (b, w); 27 U2: nand_2 PORT MAP (a, b, x); 28 U3: nand_3 PORT MAP (w, c, d, y); 29 END structural; 30 ---------------------------------------------

10 10 Example: Components Declared in a Package 1 ----- File my_components.vhd: --------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ------------------------ 5 PACKAGE my_components IS 6 ------ inverter: ------- 7 COMPONENT inverter IS 8 PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC); 9 END COMPONENT; 10 ------ 2-input nand: --- 11 COMPONENT nand_2 IS 12 PORT (a, b: IN STD_LOGIC; c: OUT STD_LOGIC); 13 END COMPONENT; 14 ------ 3-input nand: --- 15 COMPONENT nand_3 IS 16 PORT (a, b, c: IN STD_LOGIC; d: OUT STD_LOGIC); 17 END COMPONENT; 18 ------------------------ 19 END my_components; 20 --------------------------------------------- 1 ----- File project.vhd: --------------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 USE work.my_components.all; 5 --------------------------------- 6 ENTITY project IS 7 PORT ( a, b, c, d: IN STD_LOGIC; 8 x, y: OUT STD_LOGIC); 9 END project; 10 --------------------------------- 11 ARCHITECTURE structural OF project IS 12 SIGNAL w: STD_LOGIC; 13 BEGIN 14 U1: inverter PORT MAP (b, w); 15 U2: nand_2 PORT MAP (a, b, x); 16 U3: nand_3 PORT MAP (w, c, d, y); 17 END structural; 18 ---------------------------------------------

11 11 Example: ALU Made of COMPONENTS

12 12 1 -------- COMPONENT arith_unit: -------------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 USE ieee.std_logic_unsigned.all; 5 ----------------------------------------- 6 ENTITY arith_unit IS 7 PORT ( a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0); 8 sel: IN STD_LOGIC_VECTOR (2 DOWNTO 0); 9 cin: IN STD_LOGIC; 10 x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); 11 END arith_unit; 12 ----------------------------------------- 13 ARCHITECTURE arith_unit OF arith_unit IS 14 SIGNAL arith, logic: STD_LOGIC_VECTOR (7 DOWNTO 0); 15 BEGIN 16 WITH sel SELECT 17 x <= a WHEN "000", 18 a+1 WHEN "001", 19 a-1 WHEN "010", 20 b WHEN "011", 21 b+1 WHEN "100", 22 b-1 WHEN "101", 23 a+b WHEN "110", 24 a+b+cin WHEN OTHERS; 25 END arith_unit; 26 --------------------------------------------------- 1 -------- COMPONENT logic_unit: -------------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ----------------------------------------- 5 ENTITY logic_unit IS 6 PORT ( a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0); 7 sel: IN STD_LOGIC_VECTOR (2 DOWNTO 0); 8 x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); 9 END logic_unit; 10 ----------------------------------------- 11 ARCHITECTURE logic_unit OF logic_unit IS 12 BEGIN 13 WITH sel SELECT 14 x <= NOT a WHEN "000", 15 NOT b WHEN "001", 16 a AND b WHEN "010", 17 a OR b WHEN "011", 18 a NAND b WHEN "100", 19 a NOR b WHEN "101", 20 a XOR b WHEN "110", 21 NOT (a XOR b) WHEN OTHERS; 22 END logic_unit; 23 ---------------------------------------------------

13 13 1 -------- COMPONENT mux: --------------------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ----------------------------------------- 5 ENTITY mux IS 6 PORT ( a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0); 7 sel: IN STD_LOGIC; 8 x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); 9 END mux; 10 ----------------------------------------- 11 ARCHITECTURE mux OF mux IS 12 BEGIN 13 WITH sel SELECT 14 x <= a WHEN '0', 15 b WHEN OTHERS; 16 END mux; 17 --------------------------------------------------- 1 -------- Project ALU (main code): ----------------- 2 LIBRARY ieee; 3 USE ieee.std_logic_1164.all; 4 ----------------------------------------- 5 ENTITY alu IS 6 PORT ( a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0); 7 cin: IN STD_LOGIC; 8 sel: IN STD_LOGIC_VECTOR(3 DOWNTO 0); 9 y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 10 END alu; 11 ----------------------------------------- 12 ARCHITECTURE alu OF alu IS 13 ----------------------- 14 COMPONENT arith_unit IS 15 PORT ( a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0); 16 cin: IN STD_LOGIC; 17 sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0); 18 x: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 19 END COMPONENT; 20 ----------------------- 21 COMPONENT logic_unit IS 22 PORT ( a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0); 23 sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0); 24 x: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 25 END COMPONENT; 26 ----------------------- 27 COMPONENT mux IS 28 PORT ( a, b: IN STD_LOGIC_VECTOR(7 DOWNTO 0); 29 sel: IN STD_LOGIC; 30 x: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 31 END COMPONENT; 32 ----------------------- 33 SIGNAL x1, x2: STD_LOGIC_VECTOR(7 DOWNTO 0); 34 ----------------------- 35 BEGIN 36 U1: arith_unit PORT MAP (a, b, cin, sel(2 DOWNTO 0), x1); 37 U2: logic_unit PORT MAP (a, b, sel(2 DOWNTO 0), x2); 38 U3: mux PORT MAP (x1, x2, sel(3), y); 39 END alu; 40 ---------------------------------------------------

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