1. Interrupts  Interrupt is a process where an external device can get the attention of the microprocessor.  The process starts from the I/O device  The process is asynchronous.  Classification of Interrupts  Interrupts can be classified into two types:  Maskable Interrupts (Can be delayed or Rejected)  Non-Maskable Interrupts (Can not be delayed or Rejected)  Interrupts can also be classified into:  Vectored (the address of the service routine is hard-wired)  Non-vectored (the address of the service routine needs to be supplied externally by the device)

2. Interrupts  An interrupt is considered to be an emergency signal that may be serviced.  The Microprocessor may respond to it as soon as possible.  What happens when MP is interrupted ?  When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt.  Each interrupt will most probably have its own ISR.

3. Responding to Interrupts  Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not.  There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non-vectored.  Vectored: The address of the subroutine is already known to the Microprocessor  Non Vectored: The device will have to supply the address of the subroutine to the Microprocessor

4. Interrupt Vectors and the Vector Table  An interrupt vector is a pointer to where the ISR is stored in memory.  In the 8088/8086 processor as well as in the 80386/80486/Pentium processors operating in Real Mode (16-bit operation), the interrupt vector is a pointer to the Interrupt Vector Table.  The Interrupt Vector Table occupies the address range from 00000H to 003FFH (the first 1024 bytes in the memory map).  Each entry in the Interrupt Vector Table is 4 bytes long:  The first two represent the offset address and the last two the segment address of the ISR.  The first 5 vectors are reserved by Intel to be used by the processor.  The vectors 5 to 255 are free to be used by the user.

5. The Intel x86 Vector Interrupts:- Protected Mode (32-bit)  In the 80386/80486/Pentium processors operating in the Protected Mode (32-bit operation), the interrupt vector is a pointer to the Interrupt Descriptor Table.  The Interrupt Descriptor Table can be located anywhere in the memory.  Its starting address is pointed by the Interrupt Descriptor Table Register (IDTR).  Each entry in the Interrupt Vector Table is 8 bytes long:  Four bytes represent the 32-bit offset address, two the segment selector and the rest information such as the privilege level.  The first 32 vectors are reserved by Intel to be used by the processor.  The vectors 33 to 255 are free to be used by the user. ACOE255 5

7. IVT

8. ISR  While the CPU is executing a program, an interrupt breaks the normal sequence of execution of instructions, diverts its execution to some other program called “Interrupt Service Routine (ISR).  After executing ISR, the control is transferred back again to the main program which was being executed at the time of interruption.

9. Interrupt Response

10. ISR