1. EC238 MICROPROCESSORS AND APPLICATIONS

2. Syllabus Microprocessor Microprocessor Interfacing Techniques
Microcomputer communication techniques and Interfacing - Methods of parallel data transfer - Programmable parallel ports-8255 PPI - Serial communication – Asynchronous Synchronous A Programmable communication interface -DMA Programmable DMA Controller.                                                             
8259A Programmable interrupt controller Programmable Keyboard/display interface programmable interval timer     Printer Controller – 8275 CRT Controller 
Interfacing Memory and I/O Devices and Microprocessor Applications
Memory interface - Input/output Interface - -Keyboard/display interfacing -A/D and D/A interface - -Interfacing high power devices -applications -Temperature controller -Stepper motor controller – DC Motor Controller – Traffic light controller. 
8085 Microprocessor
Organization of microprocessor –Instruction set-Addressing modes- Assembly language programming-machine cycles-Read, Write – Interrupt acknowledge – Bus cycles – states – Wait state – HALT and HOLD state
8086 Microprocessor
Organization of 8086 microprocessor – memory segmentation – Addressing bytes and words – Address formation –Address modes in 8086 – Assembly language programming – minimum mode and maximum mode – Bus arbitration in minimum mode and maximum mode .  

3. EC238 MICROPROCESSORS AND APPLICATIONS
Credit:4:0:0                                                                                                                              
UNIT I : 8085 Microprocessor Organization of 8085 microprocessor –Instruction set-Addressing modes- Assembly language programming-machine cycles-Read, Write – Interrupt acknowledge – Bus cycles – states – Wait state – HALT and HOLD state                                               
UNIT II: 8086 Microprocessor Organization of 8086 microprocessor – memory segmentation – Addressing bytes and words – Address formation –Address modes in 8086 – Assembly language programming – minimum mode and maximum mode – Bus arbitration in minimum mode and maximum mode .  
UNIT III: Microprocessor Interfacing Techniques Microcomputer communication techniques and Interfacing - Methods of parallel data transfer - Programmable parallel ports-8255 PPI - Serial communication – Asynchronous Synchronous A Programmable communication interface -DMA Programmable DMA Controller.                                                             
UNIT IV: Programmable Peripheral Devices 8259A Programmable interrupt controller Programmable Keyboard/display interface programmable interval timer     Printer Controller – 8275 CRT Controller 
UNIT V : Interfacing Memory and I/O Devices and Microprocessor Applications Memory interface - Input/Output Interface - -Keyboard/display interfacing -A/D and D/A interface - -Interfacing high power devices -applications -Temperature controller -Stepper motor controller – DC Motor Controller – Traffic light controller. 

4. TEXT BOOKS
Ramesh.S.Goankar “Microprocessor Architecture, Programming &
Applications with 8085/8080a” – Penram International, Fifth Edition,1999
D.V. Hall “Microprocessor and Interfacing Programming and Hardware”,
McGraw Hill Publishing Company, 2nd Edition, 1990.

5. Reference Books
Yu.Cheng Liu & Glenn A Gibson, “Microcomputer System,8086/8088  Family”  2nd Edition, PHI, 2003
Ajit Pal “Microprocessor Principles And Applications”, Tata McGraw Hill, 1st Reprint, 2003
Avatar Singh and Walter A.Tribel “The 8088 and 8086 Microprocessor, Architecture, Software and Interface Techniques”, PHI, 1985.
Rafiquzzaman M., "Microprocessor Theory And Applications-Intel And Motorola", PHI, 2002

6. Computers Computers can able to understand only binaries
Computers Computers can able to understand only binaries. 0/1 – bit 1 byte – 8 bit 1 nibble – 4 bit 1 word – 16 bit Size: 1 KB bytes; 1 MB-2^20 bytes; 1 GB – 2^30 bytes; 1 TB – 2^40 bytes.

7. Computer
CPU
Memory
Input/output
Used to execute the
information stored in
Memory
Registers
ALU
Program Counter
Stack Pointer
Instruction decoder
Used to communicate
with CPU
RAM: Volatile Memory
ROM: Non-Volatile Memory

8. Bus
3 Types: Address Bus: unidirectional Data Bus: Bi-Directional Control bus: Read/Write Operation

9. History of Processor INTEL 4004 INTEL 8085 INTEL 8086 INTEL 80x86
PENTIUM

10. UNIT 1
8085 Microprocessor

11. Features of 8085 It is an 8-bit microprocessor
It operates on +5V power supply
It operates on clock cycle with 50% duty cycle
It has on chip clock generator
It operates at 3MHz clock frequency
It has 16 address lines, hence it can access (2^16) 64kb of memory
It provides 8-bit I/O address to access (2^8) 256 I/O ports

12. Lower 8-bit address(A0-A7) and 8-bit data(D0-D7) are multiplexed
It supports 74 instructions with 5 addressing modes.
ALU
Registers
Interrupts
Serial I/O control
Control signals (IO/ ,RD,WR)

13. PIN diagram of 8085

14. 40 20 28 21 6 19 7 8 12 9 30 29 33 34 32 31 10 35 39 36 38 11 3 37

15. Architecture of 8085

16. S – Sign Flag Z – Zero Flag AC – Accumulator Flag P – Parity Flag CY – Carry Flag

17. Interrupts
Interrupt is a process where an external device can get the attention of the microprocessor.
The process starts from the I/O device
The process is asynchronous.
Classification of Interrupts
Interrupts can be classified into two types:
Maskable Interrupts (Can be delayed or Rejected)
Non-Maskable Interrupts (Can not be delayed or Rejected)
Interrupts can also be classified into:
Vectored (the address of the service routine is hard-wired)
Non-vectored (the address of the service routine needs to be supplied externally by the device)

18. Interrupts
An interrupt is considered to be an emergency signal that may be serviced.
The Microprocessor may respond to it as soon as possible.
What happens when MP is interrupted ?
When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt.
Each interrupt will most probably have its own ISR.

19. Responding to Interrupts
Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not.
There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non-vectored.
Vectored: The address of the subroutine is already known to the Microprocessor
Non Vectored: The device will have to supply the address of the subroutine to the Microprocessor

20. The 8085 Interrupts
When a device interrupts, it actually wants the MP to give a service which is equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine)
The ‘EI’ instruction is a one byte instruction and is used to Enable the non-maskable interrupts.
The ‘DI’ instruction is a one byte instruction and is used to Disable the non-maskable interrupts.
The 8085 has a single Non-Maskable interrupt.

21. The 8085 Interrupts The 8085 has 5 interrupt inputs. The INTR input.
The INTR input is the only non-vectored interrupt.
INTR is maskable using the EI/DI instruction pair.
RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
RST 5.5, RST 6.5, and RST 7.5 are all maskable.
TRAP is the only non-maskable interrupt in the 8085
TRAP is also automatically vectored

22. The 8085 Interrupts Interrupt name Maskable Vectored INTR Yes No
RST 5.5
RST 6.5
RST 7.5
TRAP

23. 8085 Interrupts
TRAP
RST7.5
RST6.5
RST 5.5
INTR
INTA
8085

24. Interrupt Vectors and the Vector Table
An interrupt vector is a pointer to where the ISR is stored in memory.
All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT).
The IVT is usually located in memory page 00 (0000H - 00FFH).
The purpose of the IVT is to hold the vectors that redirect the microprocessor to the right place when an interrupt arrives.

25. Example: Let , a device interrupts the Microprocessor using the RST 7
Example: Let , a device interrupts the Microprocessor using the RST 7.5 interrupt line.
Because the RST 7.5 interrupt is vectored, Microprocessor knows , in which memory location it has to go using a call instruction to get the ISR address. RST7.5 is knows as Call 003Ch to Microprocessor. Microprocessor goes to 003C location and will get a JMP instruction to the actual ISR address. The Microprocessor will then, jump to the ISR location

26. Instruction Formats
Opcode: The part of the instruction that specifies the operation to be performed
Operand: The data on which the operation is to be performed
One byte Instruction
Two byte Instruction
Three byte Instruction

27. Addressing Modes Direct Addressing LDA 2040H
Register Addressing MOV A,B
Register Indirect Addressing MOV B,M
Immediate Addressing MVI B,F2H
Implicit addressing RLC

28. Instruction Set (74) Data transfer group (13) Arithmetic Group (20)
Logical Group (15+4)
Branch Group (8)
Stack, I/O and Machine control Group (2+6+6)

29. Timing Diagram
The graphical representation of the instruction execution in steps with respect to the time is called Timing Diagrams
The Fetching, Decoding and Execution of a single instruction constitutes an Instruction Cycle
Each Memory or I/O Operation requires a particular time period called Machine Cycle
Each machine cycle consists of 3 to 6 clock periods/Cycles, referred to as T-States

30. 8085 Machine Cycles Machine Cycle Status Control __ IO/M S1 S2 RD WR
____
INTA
OPCODE FETCH 1
MEMORY READ
MEMORY WRITE
I/O READ
I/O WRITE
INTR ACKNOWLEDGE
BUS IDLE

31. Representation of Signals and Signal Timings
Representation of signals: 1. Clock Signal 2. Single Signal 3. Group Signals Signal Timings: 1. ALE 2. A0- A D0- D7 4. A8- A __ IO/M, S0, S __ __ 6. RD and WR

32. Microprocessor with Memory
A15-A8
Latch
AD7-AD0
D7- D0
A7- A0
8085
ALE
IO/M RD WR
1K Byte
Memory
Chip CS
A9- A0
A15- A10
Chip Selection
Circuit

33. 8085 Machine Cycles and their Timings
1. Opcode Fetch
2. Memory Read
3. Memory Write
4. I/O Read
5. I/O Write
6. Interrupt Acknowledge
7. Bus Idle

34. OPCODE FETCH
Machine Cycle
Data Flow diagram

35. MEMORY READ
Machine Cycle
Data Flow diagram

36. MEMORY WRITE
Machine Cycle
Data Flow diagram

37. I/O READ
Machine Cycle
Data Flow diagram

38. I/O WRITE
Machine Cycle
Data Flow diagram

39. INTERRUPT ACKNOWLEDGE
Machine Cycle
Data Flow diagram

40. INTERRUPT ACKNOWLEDGE
Machine Cycle
Data Flow diagram

41. BUS IDLE
Machine Cycle
Data Flow diagram

42. BUS IDLE
Machine Cycle
Data Flow diagram

43. MVI A,30H
Machine Cycle
Data Flow diagram

44. EXAMPLES Lxi rp, data(16) MVI M, data(8) STA addr LDA addr IN addr
OUT addr

47. HALT, HOLD and WAIT State