1. Fall 2007 MIPS Datapath (Single Cycle and Multi-Cycle)

2. Fall 2007 Basic MIPS Implementation We’ll focus on a limited subset of the MIPS instructions –Memory reference: LW and SW –Arithmetic-logical: add, sub, and, or, slt –Branch: beq Hardware components: PC, registers, memory units, ALU, multiplexors, decoders

3. Fall 2007 Single Cycle v. Multi-Cycle Single cycle: one (long) clock cycle to process each instruction –not realistic but useful for understanding the implementation. Multi-cycle: divide the processing of each instruction into 5 stages and allocate one clock cycle per stage

4. Fall 2007 First 2 steps of all inst are identical 1)Send the PC to inst memory to fetch the inst 2) Read one (for LW, SW) or two registers, The next action depends on the instruction class.

5. Fall 2007 Major Functional Units What is missing? –MUX to select input data lines. –Control lines for the major functional units.

6. Fall 2007 Functional Units and Control Lines

7. Fall 2007 Fetch instruction and increment PC PC is a register that holds the current inst address

8. Fall 2007 Memory Instruction & R-type instructions * LW $t1, offset($t2), Need register file, Memory, and ALU * SW is similar

9. Fall 2007 Computing branch condition and target address

10. Fall 2007 Single cycle and control unit

11. Fall 2007 Single cycle plus jump

12. Fall 2007 1 0 0 0 10 0 0 1 Example of execution 4000 11111111111111111 000000000100000 4004 00101 00001 00110 0 4004 0 0 x x 00110 xxxxxxx 0 0 10 0 11111111111111111 00000000010000000 4004 XXXX 000000 00101 01111 10000 00000 100000 1000000000100000 10000 01111 00101 000000 100000 Instr: add $s0, $a1, $t7 Field: op rs rt rd shamt funct M. Code: 000000 00101 01111 10000 00000 100000 PC: 0 x 4000 1 10000

13. Fall 2007 Suggested Exercise Repeat the example of execution for some of these: –lw $t3, 16($t2) –sw $t3, 16($t2) –addi $t1, $s2, $v0 –beq $t3, $s0, gothere –jmp gothere –jr $ra (do them with an obsessive, detail-oriented friend)

14. Fall 2007 Multicycle Datapath Break the operations on an instruction into a series of 5 steps. One clock cycle per step –Advantage: a functional unit can be used more than once per instruction. Instruction Fetch (IF) Instruction Decode (ID) Execute (EX) Memory Access (MEM) Write Back (WB)

15. Fall 2007 Multicycle Datapath HW changes: –Single memory unit for both instructions and data –Single ALU for all arithmetic operations –Extra registers needed to hold values between each steps Instruction Register (IR) holds the instruction Memory Data Register (MDR) holds the data coming from memory A, B hold operand data coming from the registers ALUOut holds output coming out of the ALU

16. Fall 2007 Extra hardware for multicycle datapath

17. Fall 2007 Multicycle datapath

18. Fall 2007 Complete multicycle datapath

19. Fall 2007 Multicycle Datapath: the 5 steps Step NameR-TypeMemory ReferenceBranchesJumps Instruction Fetch IR <= Memory[PC] PC <= PC + 4 Instruction Decode Register Fetch A <= Reg[IR[25:21]] B <= Reg[IR[20:16]] ALUOut <= PC + (sign-extend(IR[15:0]) << 2) Execution Address Computation Branch/Jump Completion ALUOut <= A op B ALUOut <= A +……………. sign-extend(IR[15:0]) If (A==B) PC <= ALUOut PC <= ………… {PC[31:28],... …IR[25:0], 00} Memory Access R-type completion Reg[IR[15:11]] <= ALUOut Load: MDR <= Memory[ALUOut ] Store: Memory[ALUOut ] <= B Memory Read Completion Load: Reg[IR[20:16]] <= MDR