Presentation is loading. Please wait.

Presentation is loading. Please wait.

CSCE 212 Chapter 5 The Processor: Datapath and Control Instructor: Jason D. Bakos.

Similar presentations

Presentation on theme: "CSCE 212 Chapter 5 The Processor: Datapath and Control Instructor: Jason D. Bakos."— Presentation transcript:

1 CSCE 212 Chapter 5 The Processor: Datapath and Control Instructor: Jason D. Bakos

2 CSCE 212 2 Goal Design a CPU that implements the following instructions: –lw, sw –add, sub, and, or, slt –beq, j

3 CSCE 212 3 Datapath

4 CSCE 212 4 Instruction Fetch Datapaths

5 CSCE 212 5 Register File and ALU

6 CSCE 212 6 BEQ Datapath

7 CSCE 212 7 Load, Store, and R-type Datapath

8 CSCE 212 8 Combined Datapaths

9 CSCE 212 9 ALU Control ALU performs function based on 4-bit ALU_operation input Add a lookup table that instructs ALU to perform: –add (for LW, SW), or –subtract (for BEQ), or –perform operation as dictated by R-type function code Instruction opcodeALUOpInstructionFunct fieldDesired ALU action ALU control input LW00add0010 SW00add0010 BEQ01subtract0110 R-type10add100000add0010 R-type10sub100010subract0110 R-type10and100100and0000 R-type10or100101or0001 R-type10slt101010set on less than0111

10 CSCE 212 10 MIPS Datapath

11 CSCE 212 11 MIPS Datapath with Control

12 CSCE 212 12 MIPS Datapath with Jump

13 CSCE 212 13 Single-Cycle This is a single-cycle implementation Each instruction is executed within one clock cycle –Must be set for worst-case delay (LW) Instruction class Functional units used Instruction fetch Register readALU Memory access Register write R-typeXXXX LWXXXXX SWXXXX BEQXXX JX

14 CSCE 212 14 Multicycle Implementation Break instruction execution into a sequence of steps –Adjust cycle time to be long enough to perform one basic operation fetch, register read, ALU, memory access, register write –Must add registers to carry computed values from one cycle to next –Still can perform independent operations in parallel, i.e.: fetch instruction and compute next PC address read registers and compute branch address –Allows us to re-use ALU

15 CSCE 212 15 Multicycle MIPS Implementation

16 CSCE 212 16 Multicycle Control Instruction fetch –Information available: PC –Performed for all instructions –RTL: IR <= Memory[PC]; PC <= PC + 4; Instruction decode and register fetch –Information available: PC, instruction –Performed for all instructions –RTL: A <= Reg[IR[25:21]]; B <= Reg[IR[20:16]]; ALUOut <= PC + (sign-extend(IR[15:0]) << 2);

17 CSCE 212 17 Multicycle Control Execution, memory address computation, or branch completion –Information available: PC, instruction, (rs), (rt), (ALUOut) –Memory reference: ALUOut <= A + sign-extend(IR[15:0]); –Arithmetic-logical instruction (R-type): ALUOut <= A op B; –Branch: if (A == B) PC <= ALUOut; –Jump: PC <= {PC[31:28], IR[25:0], “00”};

18 CSCE 212 18 Multicycle Control Memory access or R-type completion step –Information available: PC, instruction, (rs), (rt), (ALUOut) –Load: MDR <= Memory[ALUOut]; –Store: Memory[ALUOut] <= B; –Arithmetic-logical instruction (R-type): Reg[IR[15:11]] <= ALUOut;

19 CSCE 212 19 Multicycle Control Memory read completion step –Information available: PC, instruction, (rs), (rt), (ALUOut), (MDR) –Load: Reg[IR[20:16]] <= MDR;

20 CSCE 212 20 Multicycle Control

21 CSCE 212 21 Adding Datapaths and Control How to add these instructions: –addi rt, rs, imm –bgtz rs, target –bgtzal rs, target

22 CSCE 212 22 Exceptions and Interrupts Events other than branches or jumps that change the normal flow of instruction execution –Examples: I/O device request (external, interrupt) System call (internal, exception) Arithmetic overflow (internal, exception) Invalid instruction (internal, exception) Hardware malfunction (internal or external, exception or interrupt)

23 CSCE 212 23 Interrupts and Exceptions What to do? –Execute code in response to event (handler) Save PC (EPC reg,) Record cause (Cause reg.) Set new PC (4) –Return from handler Restore PC Enable e/i (shift Status reg.) Determining type of exception –Use vectored exceptions Infer type from address –Use polled exceptions Use Cause register This is what MIPS does

24 CSCE 212 24 Example Implementation Example: –Use polled approach –All exceptions and interrupts jump to single handler at address 8000 0180 –The cause is recorded in the cause register –The address of affected instruction is stored in EPC

25 CSCE 212 25 Example Implementation

26 CSCE 212 26 Example Implementation

Download ppt "CSCE 212 Chapter 5 The Processor: Datapath and Control Instructor: Jason D. Bakos."

Similar presentations

Ads by Google