1. Performed by: Andre Steiner Yael Dresner Instructor: Michael Levilov המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט סופי Double buffer SDRAM Memory Controller Winter semester 2004 1

2. Project Description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Implementation of a device that receives a video stream from a digital video camera, performs a simple pixel processing and transfers it to a CPU through a double buffer SDRAM memory.

3. Project Goals המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Learn and experience hardware design of FPGA unit, using VHDL language Design of FPGA based system which is used as interface between a digital camera and CPU Getting familiar with SDRAM devices and learn how to activate and integrate them Design of an efficient controller for 2 SDRAM devices that will permit simultaneous reading and writing

4. System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 4 Pixel Processing Unit SDRAM controller write part SDRAM controller read part Data Bus Control signals CPUFPGA CAMERA FIFO Switch SDRAM A SDRAM B

5. System Description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 The digital camera with an internal clock of 100MHZ and this clock is supplied to the system. The camera sends a stream of 1024 pixels and then stays idle for 2us. Each grayscale pixel is size of a bit. Every 10ns a pixel is sent. The system supports a CPU, whose clock is similar to the camera’s and asks for the data randomly The system is made to function with unsynchronized clocks and can support differences of the frequencies.

6. Main Conclusion המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 The important factor that influences the system’s performance is the CPU. As closer the CPU clock is to the camera’s, as better the system’s performance will be. This directly affects the time that the system will work and the size of the pixels stream that can be sent without overflow.