1. 1 Omar F. Mousa Professor: Scott Wakefield Omar F. Mousa Professor: Scott Wakefield

2. 2PreparationPreparation  There are two shells in Unix:  C shell and appears with % prompt and.cshrc is associated with it. If you use the C shell, add the following to your.chsrc file: source/usr/local/scripts/setup.synopsys- 2000.11.csh. Remember to execute  $ source.cshrc  Bourne Shell and appears with $ prompt and.profile with associated with it. If you use the Bourne shell, add the following to your.profile file: setup synopsys-2000.11  Remember to execute  $..profile

3. 3PreparationPreparation

4. 4PreparationPreparation  Prepare a HDL (either in Verilog or VHDL) design. It is better to partition the design to speed up optimization run times, so that each block contains about 250 to 5000 gates. 3. As an example, say your design's name is "mychip", do the following steps :- $ mkdir mychip $cd mychip $ mkdir work $ mkdir src $ mkdir db

5. 5PreparationPreparation 4. Create a file named.synopsys_dc.setup (use exactly the same name), and put it in mychip directory.  A sample of mychip/.synopsys_dc.setup file looks like the following: designer = "Mr. Tiny Chips" company = "Less is More, Inc." search_path = {".", "/app_annex01/synopsys- 2000.11/libraries/syn"}+ "./src" + "./db“ link_library = {"*", "class.db"} target_library = "class.db" symbol_library = "class.sdb" define_design_lib WORK -path./work

6. 6PreparationPreparation Where: The default search_path is everything between double quotes "{".", "./app_annex01/synopsys-2000.11/libraries/syn"}", this tells the Design Compiler to search for files or db at the current directory and at the libraries/syn directory where all the vendor libraries sources and db are placed. Instead of using class.db as your library, you can navigate to that libraries/syn directory, choose your preferred technology library and replace the above library assignment.

7. 7PreparationPreparation  The link_library is used to define any technology input to the synthesis process, the "*" is necessary as it tells the Design Compiler to search for the existing databases in the Design Compiler memory first.  The target_library is the technology library to which you map your design during optimization.

8. 8PreparationPreparation  The symbol_library contains graphical data used to draw the symbols for the cells of the target or link libraries.  A design library is a logical name referring to a UNIX directory which will store the intermediate files (the.mra.sim... files) produced by analyze so as to not clutter up your present directory. You can choose other descriptive name besides work.  Put.synopsys_dc.setup file in your working directory (use exactly the same file name).

9. 9 Failure Mechanisms 5. Create a file called.synopsys_vss.setup below and put it in your working directory (use exactly the same file name ).

10. 10PreparationPreparation  The file content is : CY_CCPATH=/usr/bin/cc CY_CCPATH=/usr/bin/cc WORK > DEFAULT DEFAULT : VHDL library to UNIX dir mappings -- SYNOPSYS:$SYNOPSYS/$ARCH/packages/synopsys/lib IEEE : $SYNOPSYS/$ARCH/packages/IEEE/lib

11. 11PreparationPreparation

12. 12 6. Place your HDL or verilog source files under the mychip/src directory

13. 13 7. Place your HDL or verilog test bench source files under the mychip/src directory too

14. 14

15. 15SimulationSimulation Run VCS to simulate your design $ cd src/ $ vcs add_sub.v tb_add_sub.v After that, an executable file will be created called simv as shown below. To view the results… Type $simv

16. 16SimulationSimulation

17. 17Simulation-ResultSimulation-Result bash-2.03$ simv Chronologic VCS simulator copyright 1991-2000 Contains Synopsys proprietary information. Compiler version 5.2; Runtime version 5.2; May 5 18:18 2003 stim_A= 8, stim_B= 5, stim_add_sub_sel=0, sum_out=13, carry_out=0 stim_A=14, stim_B= 1, stim_add_sub_sel=0, sum_out=15, carry_out=0 stim_A=10, stim_B=11, stim_add_sub_sel=0, sum_out= 5, carry_out=1 stim_A= 8, stim_B= 5, stim_add_sub_sel=1, sum_out= 3, carry_out=1 stim_A=14, stim_B= 1, stim_add_sub_sel=1, sum_out=13, carry_out=1 stim_A=10, stim_B=11, stim_add_sub_sel=1, sum_out=15, carry_out=0 $finish at simulation time 376 V C S S i m u l a t i o n R e p o r t Time: 376 CPU Time: 0.110 seconds; Data structure size: 0.0Mb Mon May 5 18:18:46 2003

18. 18 Analyze & Elaborate  Go back to your mychip directory

19. 19 Analyze & Elaborate  To invoke Design Analyzer, enter the following at the directory mychip : $ design_analyzer & After the tool is finished initializing, the Design Analyzer window will pop up as shown in Figure. Note : the directory where you invoke design_analyzer would contain the command.log file which lists the commands executed. Note : the directory where you invoke design_analyzer would contain the command.log file which lists the commands executed.

20. 20 Analyze & Elaborate  Verify that your.synopsys_dc.setup file was executed by selecting  Setup (Menu) -> Defaults (Submenu )

21. 21 Analyze & Elaborate Press OK

22. 22 Analyze & Elaborate Select Setup -> Command Window to bring up the window that gives you access to dc_shell and also immediate feedback on the progress of your synthesis session. Resize it and drag it to the appropriate place in your display. All commands entered via the menus of the Design Analyzer are echoed, so you can learn how to write dc_shell scripts later on.  Select File -> Analyze,

23. 23 Analyze & Elaborate Double click on the src directory to see the appropriate files. Select the appropriate format for File Format, click on WORK in the Library box, and click OK.

24. 24 Press OK

25. 25  If no errors click Cancel

26. 26 Analyze & Elaborate 5. Inspect the messages in the Analyze window, correct any syntax errors in your HDL files and do the analyze again, otherwise, cancel the Analyze window and proceed. 6. Select File (Menu) -> Elaborate (Submenu), select WORK from the Library box, select your "top level design" from the Design box, and click OK. Elaboration brings all the associated lower level blocks into the Design Compiler automatically (by following the dependency of the instantiations within the HDL code). After the elaboration is done, cancel the Elaborate window.

27. 27

28. 28 Press OK

29. 29 Adder and Subtractor: By double clicking on the yellow box

30. 30 Adder and Subtracter

31. 31 Adder and Subtrator

32. 32 Adder Subtractor

33. 33 Analyze & Elaborate The equivalent dc_shell command will be: dc_shell>elaborate module_name -arch "verilog" -lib WORK -update  Instead of doing Analyze & Elaborate, you can also do just Read for a HDL design, the difference is that you have a choice of design library to place the analyzed design when you do Analyze, whereas with Read only the default library WORK is used. Your design is now translated to a technology independent RTL model.

34. 34 1. On the left side of the Design Analyzer window are the View buttons. The top 4 buttons select the type of view: Design, Symbol, Schematic or Text. The bottom 2 buttons are used to traverse the hierarchy of a design. Select the icon for your top level design block, say CONTROL, by clicking on it, the border of icon is shown as a dashed line instead of a solid line, the design is now CONTROL, as seen in the lower left corner of the Design Analyzer window. Applying Constraints

35. 35 2. Double click on the CONTROL icon and this will produce the Symbol View. The Symbol View is convenient for applying attributes and constraints to a design. Click on the appropriate port and select from the Attributes menu your desired constraints. If your design has a clock port, you have to select Dont Touch Network in the Specify Clock window, Synopsys does not effectively synthesize clock tree. Do not highlight a port if you want to create a virtual clock. 3. You can check for missing files by selecting from the main menu, Analysis -> Link Design

36. 36 Press OK

37. 37 Press Cancel

38. 38 Applying Constraints  The link command checks to make sure all parts in the current design are available in Design_Analyzer's memory. If there is a missing part ( also known as unresolved reference) you have to read in the file that contains the missing part.  Note: If the missing part is saved as a.db file it is read in automatically during the execution of the link command.  Note: If the missing part is saved as a.db file it is read in automatically during the execution of the link command.  After the link is done, cancel the Link Report window.  The equivalent dc_shell command will be:  $dc_shell> link

39. 39 Applying Constraints 4. To check your design's netlist description for problems like connectivity, shorts, opens, multiple instantiations select, Analysis (Menu) -> Check Design(Submenu)

40. 40 Applying Constraints Click OK

41. 41

42. 42 Applying Constraints You can also check for potential timing problems (i.e. no clocks specified, outputs unconstrained for time) by clicking on Check Timing. After the Check Design is done, cancel the Design Errors window. The equivalent dc_shell command will be: $dc_shell>check_design 5. You may also select Analysis (Menu)-> Report (Menu) -> Port (From Dialogue Box)

43. 43  Click on Timing Requirements to generate a report to verify port attributes and delay constraints.

44. 44 Applying Constraints

45. 45 Applying Constraints After the Report is done, cancel the Report window. The equivalent dc_shell command will be: $dc_shell>report_port $dc_shell>report_port 6. To set area constraint, select Attributes -> Optimization Constraints -> Design Constraints and use this dialog box to set design objectives for the top-level of a design. The name of the top level is displayed in the Design Name field. Note that the units of area, time, capacitance are defined by the vendor. To find out about the contents of a technology library, type the following commands in the command window :- Read library name.db report_lib library name where library name is the target library (without the '.db' extension). e.g: read class.db

46. 46 report_lib class. The equivalent dc_shell command will be: $dc_shell>max_area “number” $dc_shell>max_area “number” $dc_shell>max_power “number” $dc_shell>max_power “number” $dc_shell>set_max_fanout $dc_shell>set_max_transition 7. There is no menu option for set_driving_cell in Design Analyzer. Enter the command in the command window. It is in the following format : $ set_driving_cell -library libname -cell cellname -pin pinname portlist.  If no -library specified, default is the link library.  Pin is required only when the driving cell has more than 1 output pin. Applying Constraints

47. 47 Applying Constraints $ set_driving_cell -cell "INV" all_inputs() - CLK  The inputs (except for the port CLK) are driven by the "INV" cell found in the link library. 8. At this point you may save your design as an unmapped db format, select File -> Save As, navigate to the./db directory in the Directory menu, and name your design as control_unmap.db, choose DB as the File Format. When a design is saved as a.db file, the design plus all attributes are saved. The equivalent dc_shell command will be: $dc_shell>write -format db -hierarchy -output "/entire_path_name/module_name_unmap.db" {"/entire_path_name/module_name.db:module_n ame"}

48. 48 Applying Constraints 9. Next time you want to retrieve the already elaborated but unmapped design,  you could select File -> Read with DB as file format. You can enter reset_design in the command window to remove all attributes and apply new attributes if needed.

49. 49OptimizationOptimization  If your design contains hierarchy, it is recommended to use the Bottom-Up Hierarchical Compile approach (Note : in Synopsys, compile = synthesize = optimize). Compile sub-blocks independently, but do not compile the top level design.  Select Tools -> Design Optimization, the default Map Design setting is Medium.

50. 50OptimizationOptimization Then click on OK, it might take a few hours or even more than a day to compile. Do not apply other options in your first compile run.

51. 51OptimizationOptimization  When the optimization is complete, a Cancel button located at the bottom of the  Compile Log Window will become "grayed in" indicating that you can cancel the window and view your results.  Press OK

52. 52OptimizationOptimization After linking to the library and compiling, Press CANCEL

53. 53

54. 54 Inspection of Results 1. Notice the changes in any icon of your design, it is now optimized to gate level, double click on the icon to reach the Symbol View, then click on the Schematic View button to inspect the design. Select View -> Zoom In (or press Control-V) to zoom in. 2. You can select pin(s) or port(s) from the design, then select from Analysis -> Highlight a type of highlighting to see the path to the pin or port. Press Control-T is a shortcut to highlight the critical path. 3. Select a design block (the top level design if your design is hierarchical), do Analysis -> Report, click on Area, Timing, you could direct the output to a file for later reference. Inspect the Report Output window, use the mouse to select a line, click on the Next button, the item(s) in the corresponding schematic will be "selected" automatically.

55. 55

56. 56 Press Apply

57. 57  The equivalent dc_shell command will be: $dc_shell> report_area $ dc_shell> report_timing $ dc_shell> report_timing 4. Inspect the timing report, each Incr entry indicates the delay from the previous point to the current point, and the Path entry indicates the total delay from the input external delay to the current point. You can detect any suspicious path with exceptional long delay through this inspection. The most important thing is to check the slack, which is the required delay minus the actual delay, if it reports MET, your design has met the timing constraints, if it reports VIOLATED, you should go back to your HDL code and re-write it to improve timing. Then go back and re-analyze -elaborate the block and compile the whole design again.

58. 58 Save & Quit 1. Save your design by selecting File -> Save As, navigate to the.db directory in the Directory menu and choose DB as the File Format, it is recommended to use the Save All Designs in Hierarchy option.

59. 59 You can save the file anywhere you want…. Double click the db directory and save the add_sub.db

60. 60Saving Press OK

61. 61 Saving Your File as Netlist  You can save the verilog file (Netlist file) the same way…. In your scr/ directory, create this file and make sure to change the file format to VERILOG as shown below  Press OK 2. You might want to read in another design without quitting Design Analyzer, you could first remove the current design by selecting the design to be removed, then Edit -> Delete. This would remove the design from the Design Compiler memory, it would not remove any physical design files.  To quit the Design Analyzer, select File -> Quit and click OK.

62. 62 FIR Filter

63. 63 FIR Filter