1. Kuno-Group B4 Yuuki Matsumoto A report for Graduation research Development of Trigger Board for MPPC (for MuSIC experiment) A report for Graduation research Development of Trigger Board for MPPC (for MuSIC experiment)

2. Contents 1.Back Ground & Purpose 2.Equipment 3.Experiment 4.To do (Plan)

3. 1.Back ground &Purpose Strong magnetic field Use MPPC for measurement of Muon(8×10 8 /sec) using scintillation counter. Complex circuit is needed to readout MPPC signal. SPIROC-A board can perform all part. here I develop SPIROC-A board for MPPC

4. 2.Equipment signal from MPPC HVadd and change logic circuit from PC send command from PC EASIROC Analog out hold NIM out SPIROC-A board FPG A I use right board The board, @MPPC 32ch can drive at the same time. @It has ADC. @We can program FPGA to use TDC. @It has not have TDC yet. @Clock output < 334MHz @Clock jitter ±100 〜 ±150ps @The board is a new test board, so we don’t know clearly how to use.

6. Low Gain Pre Amp High Gain Pre Amp Discri OR32 Hold Read Hold Read ADC1ADC1 ADC1ADC1 ADC2ADC2 ADC2ADC2 V_th 1.5pF 15pF Read EASIROC 25—175ns 15ns

7. 3.Experiment 1.I measured ADC spectra from Function Generator. 2. I measured ADC spectra from MPPC.

8. @measured ADC spectra from Function Generator pink : direct signal from Function Generator(80mV 25ns) blue : high gain after slow shaper cyan : low gain after slow shaper no holdhold

9. ADC spectra ( Function Generator gave 80mV 25ns pulse ) High gain Low gain phed = 975 ch

10. ADC peak ch and input charge mV50 60708090100110120 ns510152025 pC51015202530354045505560 peak133717152098247328213187345835693607362236303636 RMS18.6518.518.3518.2717.7416.218.2824.1243.6853.1532.7822.446 [pC]=[mV]×[ns]÷[50Ω] Linear shaper is down Δch=73.96 ΔpC

11. @measured ADC spectra from MPPC Dark current Hold is OR32. In oscilloscope, there are many hold from other ch. It may make noises. 1 photon?? 2 photon?? What?? Now, examining

12. 4. To do 1measure MPPC spectra using LED 2measure resolution and delay of discriminator 3measure TDC spectra (extra TDC) 4write TDC program to FPGA in VHDL 5measure TDC spectra (internal TDC) counter (FPGA) counter (FPGA) Discri clock STOP Signal from outside START PC time resolution <1000/334 = 2.99ns muon life time is 2μs

13. END