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Veto Wall Test Hyupwoo Lee MINERvA/Jupiter Group Meeting Feb, 13, 2008.

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Presentation on theme: "Veto Wall Test Hyupwoo Lee MINERvA/Jupiter Group Meeting Feb, 13, 2008."— Presentation transcript:

1 Veto Wall Test Hyupwoo Lee MINERvA/Jupiter Group Meeting Feb, 13, 2008

2 Noise problem in pedestal study

3 3 Pedestal Use two different way for taking pedestal data - Pedestal Mode : without hit (Jesse’s note) - Discriminator Mode : with trigger hit (random trigger) Pedestal - (board offset) + (board noise) + (PMT noise) Open channel : without PMT signal => only about board PMT channel : with PMT signal (with 3-ch wire divider) => board and PMT

4 4 Setup – 1 (TriP-t register setting) Pedestal Mode - Without hit - Without firing discri. - Same condition for real data? Discriminator Mode - Need trigger hit - Use random trigger - Almost same condition for real data - Need more time for all channel - I will choose this mode for future pedestal data taking

5 5 Setup – 2

6 6 Open & PMT 1 (same channel – discri. mode) Gaussian fit with selected interval Gaussian fit with whole interval This tail makes problem

7 7 Where the noise comes from? - Lots of pain for me Light leakage? - I tried with turning HV off : the same noise appears. Noisy HV supply? - I tried to disconnect HV supply : the same noise appears. Noisy PMT circuit? - I tried with the other PMTs (from the small panels and opposite side PMT) : the same noise appears. Floating ground? - I checked all, found a floating ground from low voltage supply, and fixed it : the same noise appears. I found something wrong with high-gain.

8 8 Double peak at high-gain No signal input for all 16 channels All high-gain channels have double peak problem. Their correlation seems like phase related something. (Paul has not seen yet this correlation.) Paul suspects that the noise comes from PC via signal cable Paul suggests to connect FEB’s ground to the other ground-stuff with thick grounding cable.

9 Ratio of ADC counts to Q

10 10 Setup – 1 (TriP-t register setting)

11 11 Setup – 2 Square pulse(+) for circuit varied from 0.5V to 5V (with 50 Ohm load) Signal input varied from 0.5pC to ~5pC RC time for signal input ~5ns Signal size : ~30pC(average) from the scope calculation of the last summer research Over than 5pC ? - >100pF : RC time ? - new combination of resistors (I will try) - >5V square pulse (possible to 10V, I will try)

12 12 Setup – 3 (Signal timing) Purple : GATE Blue : Charge injection square pulse Yellow : TRIG Time interval between square pulse edge and TRIG : ~50ns

13 13 Result - 1 Low-gain seems no problem but high-gain has the same double-peak problem

14 14 Result - 2 High-gain results seems to be affected by saturation over than 3pC. Linearity doesn’t hold at low-gain when high-gain is saturated. 46fC(4.6fC)/ADC count for low(high)-gain within the linear region. The y-intercept at low-gain shows the same value as pedestal result.

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