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Computer Organization Lecture 19
Exam 2 results Project 4: Memory Microprogramming: R-type Lillevik f06-l19 University of Portland School of Engineering
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Exam 2 statistics Prob Std Ave 1/10 2.3 7.7 2/10 2.7 7.8 3/10 0.7 9.8
4/10 3.0 6.4 5/10 1.9 8.8 6/10 1.2 9.6 7/10 2.2 8.7 8/10 3.7 9/10 8.3 10/10 8.5 12.9 77.8 Lillevik f06-l19 University of Portland School of Engineering
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MIPS controller From Lecture 12 & 17 Outputs Outputs Inputs IR(31:25)
Lillevik f06-l19 University of Portland School of Engineering
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FSM architecture Present State NS Decoder Output Inputs Outputs ROM
Combo logic Flip Flops Lillevik f06-l19 University of Portland School of Engineering
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Project 5: Memory Memory contains ROM and RAM
Size: 16K words ROM: first 256 words RAM: remaining 16K words Not installed: 17K – 64K words Due: Wednesday, November 17 Lillevik f06-l19 University of Portland School of Engineering
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Requirements Address Map Inputs Outputs Address Memory Input Function
0x000 – 0x0ff ROM 0x100 – 0x3fff RAM 0x4000 – 0xffff No memory installed Address Map Input Function ADR Contains a 16-bit address to access the memory Din Contains a 16-bit data to write into the memory MEMwr When asserted, data is written to the memory Inputs Output Function Dout Contains 16-bit data read from the memory Outputs Lillevik f06-l19 University of Portland School of Engineering
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MicroAsm Java application: MicroAsm.class, SavitchIn.class
Microinstruction: free format, no fixed fields Requires input file: text-only, file.upg Creates output file: file.txt Errors: command line file name, file I/O, unrecognizable token Execution: BlueJ or DOS command line Lillevik f06-l19 University of Portland School of Engineering
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uProgram tokens Token Value Function Branch 0000 0100
Branch the uPgm to the opcode (default is next address) Rwr Write to the REG file Imm uPgm controls ALU function (default is IR[3:0]) PCinc Increment the PC PCwr Write to the PC PCwrcond Write to the PC if EQ is asserted EPC Select EPC for PC write IoD Select RALU for memory address (default is PC) MEMwr Write to the memory (default is to read) IRwr Write to the IR MDRwr Write to the MDR Lillevik f06-l19 University of Portland School of Engineering
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uProgram tokens, continued.
Value Function SPCwr Write to SPC register PCsrc PC write data is branch address (default is jump address) ALUa-R0 ALUa-PC First ALU argument is R0 First ALU argument is PC (default is PC) ALUb-R1 ALUb-Ext ALUb-Trnc Second ALU argument is R1 Second ALU argument is Sign Extended offset Second ALU argument is Truncated offset REG-RALU REG-MDR REG write data is the RALU REG write data is the MDR Lillevik f06-l19 University of Portland School of Engineering
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uProgram tokens, continued.
Value Function REGfmt Selects IR[10] for the REG destination (default is IR[9]) ALUOpadd ALUOpsub ALUOpand ALUOpor ALUOpsll ALUOpsrl ALU function is add ALU function is subtract ALU function is logical AND ALU function is logical OR ALU function is shift left logically ALU function is shift right logically Next Return uPC+1 00 Inserts uPC+1 into uPgm next address (default) Inserts 00 into uPgm next address Lillevik f06-l19 University of Portland School of Engineering
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MDP16 state diagram ID sll sw srl lw j IF Reset 2 clocks
nop R-fmt sw srl lw addi beq j ori subi andi IF Reset 2 clocks 1- 3 additional clocks Lillevik f06-l19 University of Portland School of Engineering
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IF/ID states Write instruction from memory into IR, Increment the program counter (clock 1) Determine optimistic branch address Dispatch to opcode (clock 2) IRWr PCinc Alua-pc Alub-ext imm aluopadd branch Lillevik f06-l19 University of Portland School of Engineering
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R-type microprogram Func bits (IR[3:0]) determine ALU operation (clock 3) Write result into register file (clock 4) Rwr reg_Ralu Return aluA_R0 aluB_R1 Lillevik f06-l19 University of Portland School of Engineering
![R-type microprogram Func bits (IR[3:0]) determine ALU operation (clock 3) Write result into register file (clock 4)](http://slideplayer.com/slide/17186028/99/images/13/R-type+microprogram+Func+bits+%28IR%5B3%3A0%5D%29+determine+ALU+operation+%28clock+3%29+Write+result+into+register+file+%28clock+4%29.jpg "Rwr. reg_Ralu. Return. aluA_R0. aluB_R1. Lillevik 333f06-l19. University of Portland School of Engineering.")
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R-type microprogram Lillevik 333f06-l19
University of Portland School of Engineering
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MDP16 state diagram ID sll sw srl lw j IF Reset nop beq addi ori subi
R-fmt sw srl lw addi beq j ori subi andi IF Reset Lillevik f06-l19 University of Portland School of Engineering
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Sll instruction ALU function is shift left logically
Write result into register file Lillevik f06-l19 University of Portland School of Engineering
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Sll EX state? Origin: 0x20 Operation: clock 3 Functional units
RALUout = A << 1 Functional units uPgm must control ALU function ALU funct = shift left logically ALU input R0 Lillevik f06-l19 University of Portland School of Engineering
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Sll WB state? Next: return to IF Operation: clock 4 Functional units
Reg [ IR(10)] = ALUout Functional units Must write to reg file Data comes from RALU Use IR[10] as destination register Lillevik f06-l19 University of Portland School of Engineering
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MDP16 state diagram ID sll sw srl lw j IF Reset nop beq addi ori subi
R-fmt sw srl lw addi beq j ori subi andi IF Reset Lillevik f06-l19 University of Portland School of Engineering
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Store instruction Find the effective address
Write register contents to memory Lillevik f06-l19 University of Portland School of Engineering
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Store EX state? Origin: 0x50 Operation: clock 3 Functional units
ALUout = A + sign-extend (IR[0:9]) Functional units uPgm must control ALU function ALU funct = add ALU inputs R0 Sign-extended offset Lillevik f06-l19 University of Portland School of Engineering
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Store MEM state? Next: return to IF Operation: clock 4
Memory [ALUout] = B Functional units RALU addresses memory R1 written into memory Lillevik f06-l19 University of Portland School of Engineering
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Completed Microcode ROM
Lillevik f06-l19 University of Portland School of Engineering
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Lillevik f06-l19 University of Portland School of Engineering
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Sll microprogram ALU function is shift left logically (clock 3)
Write result into register file (clock 4) Rwr reg_Ralu regFmt Return Imm aluA_R0 aluOpSll Lillevik f06-l19 University of Portland School of Engineering
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Sll microprogram Lillevik 333f06-l19
University of Portland School of Engineering
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Store microprogram Find the effective address (clock 3)
Write register contents to memory (clock 4) Imm aluA_R0 aluB_ext aluOpAdd IoD MemWr return Lillevik f06-l19 University of Portland School of Engineering
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Store microprogram Lillevik 333f06-l19
University of Portland School of Engineering
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